Abstract: A differential amplifier circuit used to test the underlying DRAM memory cells in large area spatial light modulator (SLM) arrays by significantly increasing the cell capacitance to bitline capacitance ratio. Since for these SLM devices it is not desirable to sub-divide the DRAM array into smaller test arrays in order to reduce the bitline capacitance, this invention addresses the bitline capacitance problem by reading the differential voltage between two adjacent cells rather than the actual voltage of each cell. The approach is to load, precharge, and readout a checkerboard pattern and then repeat the process for an inverse checkerboard pattern. Cell outputs which have the same value for the two complimentary patterns indicate a cell failure. In this approach, the cell differential voltage readout is effectively doubled to approximately ±200 mVolts, providing 100% test coverage of these large area arrays. This results in an effective DRAM test procedure which is independent of bitline capacitance.

Abstract: A method of addressing an array of spatial light modulator elements. The method divides the array into blocks of elements, provides reset lines (MRST) to each of the block of elements, separate from the other blocks of elements, as well as address voltage supplies (VCCADDR) to each of the block of elements, separate from the other blocks of elements, addresses data to each of the blocks independent of the other blocks, resets each of the blocks, and steps address voltage to each of the block, where only blocks that are being reset receive the stepped address voltage. A spatial light modulator array (32) is also provided that has a layout to facilitate the method, including internal or external circuitry (34) to provide control of the stepped addressing voltages.

Abstract: A folding differential amplifier includes a switching preamplifier used to select between first and second differential amplifiers as a function of an input signal. The switching preamplifier includes first and second outputs that are coupled together by a first shorting switch having an open phase and a closed phase. The first and second outputs are held at a steady state value during the closed phase of the shorting switch and allowed to vary during the open phase of the shorting switch. First and second differential amplifiers each have first and second outputs and the first output of the first differential amplifier is coupled to the second output of the second differential amplifier. Similarly, the second output of the first differential amplifier is coupled to the first output of the second differential amplifier. These cross coupled outputs form first and second amplifier outputs respectively.

Abstract: A full-wave rectifier circuit (500) includes a cross-coupled differential pair circuit (501) coupled to a bias circuit (510). At least one constant current source (512, 514) couples to the base of each transistor (506, 508) in the cross-coupled pair circuit (501). A differential pair of transistors (502, 504) drive the cross-coupled pair circuit (501). Cross-coupled devices (506, 508) are used as positive feedback to increase gain for small amplitude signals and to degenerate the devices (502, 504) of the full-wave rectifier. Using this design very precise rectification can be achieved even for &thgr;i<VT. Specifically, the bias circuit (510) includes a current source which supplies &agr; multiplied by the current supplied by the current source (512, 514) connected to the base of the transistors (506, 508) in the cross-coupled pair circuit (501). By choosing an appropriate value of &agr;, a unity magnitude slope close to the origin is achieved.

Abstract: A low voltage 485-driver circuit that meets the standard leakage and 1.5 voltage differential output requirements of the TIA/EIA-485 specification while operating from a 3V supply. The circuit avoids the voltage drop across the series Schottky diodes in the output driver of a conventional 485-driver by moving the Schottky blocking diodes from the output stage signal path to the pre-driver stage so that the output stage is restricted to back-gate biasing only. In addition, the circuit uses stacked NMOS transistors to maintain lower voltage across each NMOS transistor in order to prevent hot-carrier injection. This allows lower voltage rated output NMOS transistors to be used, resulting in higher speed operation. The circuit will withstand excessive common mode voltages in the range of +12V to −7V applied to the output while in either signaling ON state or the disabled OFF state.

Abstract: Improved approaches to provide flexibility in setting user data rates and managing delay in data transmission systems using a superframe structure and Time Division Duplexing (TDD) are disclosed. These improved approaches operate to provide intelligent insertion of dummy words (bits or bites) into a data stream to be transmitted. By inserting the dummy words, the invention is able to render codewords, symbols and superframes independent from user data rates. As a result, a wide range of user data rates are available in data transmission systems using a superframe and TDD.

Abstract: A circuit is designed with an encoder circuit (602) coupled to receive a data sequence. The encoder circuit produces a first encoded data sequence and a second encoded data sequence from the data sequence. A first spreading circuit (606) is coupled to receive the data sequence and the first encoded data sequence. The first spreading circuit produces a first modulated data sequence in response to a first code. A second spreading circuit (614) is coupled to receive the data sequence and the second encoded data sequence. The second spreading circuit produces a second modulated data sequence in response to a second code.

Abstract: A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the formation of the LDD regions 180, 220, and the pocket regions 190, 230 of the core transistors 152, 154. The LDD regions 240, 200 of the I/O or analog transistors 156, 158 are simultaneously formed during the process.

Abstract: The present invention provides a hardware assisted automatic gain control (AGC) for a communication network. A dedicated hardware portion of the AGC, which works in cooperation with software implemented functionality (400), is included to detect saturation conditions in the internal nodes of the analog front end (200) in which a plurality of gain stages (PGA1, PGA2, PGA3) and filter stages (H1, H2, H3) are interleaved with inaccessible intermediate points. The saturation detection logic includes a comparator (21, 22, 23) and flip-flop (27, 28, 29) for each gain stage (PGA1, PGA2, PGA3) and can be integrated directly in the analog front end 200. The dedicated hardware can further be included in a codec of a modem in a digital subscriber line (DSL) system.

Abstract: A TDMA system in which the mobile receiver performs unique word detection (and hence frame synchronization) by using real correlation coefficients which are not equal to the binary unique word (nor to any shift or scaling of it), but which are dependent on the unique word. In some embodiments, the correlation coefficients are dependent both on the unique word and also on the bit_sync pattern.

Abstract: In an equalizer filter unit, the filter is divided into a plurality of sequential segments. While all the components of the equalizer unit multiply data signal groups by the a coefficient signal group, in only one segment are the coefficient signal groups updated. The data and the coefficient signal groups are periodically transferred to the next sequential filter segment while the filter segments are reconfigured in the original sequential order. In this manner, the each data signal group interacts with a coefficient signal group in the original sequential order. Because the coefficients are updated in only one of the filter segments, the amount of apparatus required for processing signal groups is reduced.

Abstract: An algorithmic procedure automatically generates layout of matched capacitor arrays used in A/D converters, D/A converters and programmable gain amplifiers, among other types of devices, using templates to define the style of the layout. Since each array can be generated from a particular template, multiple arrays associated with an IC can be optimized for different purposes to preserve silicon area. The automated technique allows fast and easy migration of an array layout from one process to another and eliminates the manual design work generally associated with capacitor array layout.

Abstract: An electric circuit breaker (10) has a toggle mechanism (18) having two movable over center joints (3, 4) connected between a push-button (16) and a movable contact mechanism (30). When the push-button is depressed a first link rotates bringing the first movable over center joint (3) across a center position represented by a first imaginary straight line (1) to a stop surface (28). A spring member (36) provides a bias which acts on the second movable over center joint (4) normally maintaining the second movable joint against the stop surface so that with the two movable over center joints biased against the stop surface the movable contact mechanism is moved to a closed contact position when the push-button is depressed.

Abstract: A method and apparatus for improving the AC common mode rejection performance of monolithic two op-amp instrumentation amplifiers is disclosed. A new approach to designing the first op-amp of an instrumentation amplifier is provided wherein the frequency of the first op-amp is manipulated such that the dominant pole is pushed out to higher frequencies than is possible using traditional methods while maintaining good open loop gain and closed loop stability. One way to achieve this is by designing the first op-amp such that it has two dominant, low frequency poles and a higher frequency zero to provide stability. With this design of a first op-amp, the range of high common mode rejection ratio is extended to frequencies an order of magnitude higher than achievable by conventional means without additional requirements for bandwidth, power or die area.

Abstract: A projection display that combines both overhead projector and electronic display functionality in a single projector. This invention provides a single comprehensive solution, which addresses both overhead projection display needs, as well as electronic projection display needs and further provides a new function that allows superimposed images from the two functions to be captured and stored for future projection through the electronic display function.

Abstract: A structure (10) is provided that is fabricated as a ball grid array substrate that includes a substrate dielectric (14), a power ring (18), a ground ring (20), a plurality of traces, and a second metal layer (16). The substrate dielectric (14) includes a first side, a second side, and a cavity formed therein. The power ring (18), the ground ring (20), and the plurality of traces are provided on the first side of the substrate dielectric (14). The plurality of traces, for example, may include a signal connection (22), a ground connection (24), and a power connection (26). The second metal layer (16) is provided on the second side of the substrate dielectric (14) and is electrically coupled to the first side. For example, the second metal layer (16) may serve as an active ground plane and electrically couple to a variety of ground connections, such as the ground connection (24), and the ground ring (20) through vias in the substrate dielectric (14).

Abstract: A power supply (500) with vertical field effect transistor synchronous rectifiers (VFET1 and VFET2) having drivers (VFET Driver1 and VFET Driver2) which provide bipolar mode of operation by diode clamping an inductor overshoot which forwards biases the gate-source junction. The rectifiers have low on resistance useful in low output voltage power supplies.

Abstract: A method for prioritizing protection in the symbol mapping of selected information includes the steps of supplying information bits and overhead bits. Interleaving the information bits and overhead bits to supply a plurality of interleaved data blocks. And selectively mapping the plurality of interleaved data blocks into a modulation symbol.

Abstract: A circuit and method are provided for accurate and adjustable current limiting/sensing in a power IC (100). In particular, a current limiting/sensing circuit (110) and method of use are provided that substitutes a transistor (MD2) in place of a resistor. Consequently, all of the components (MD1, MD2, MDout) in the IC (100) may be identical transistors, which may be fabricated by one process and integrated in one power structure. Therefore, process variations from device to device and errors due to thermal gradients between components may be minimized, thereby reducing the complexity and fabrication costs of the power ICs. Additionally, a user may readily adjust the trip/sensing point of the current limiting circuit (110) without having to physically alter individual components in the IC (100).

Abstract: An Automatic Gain Control System for voice codecs used in a digital wireless handset or in any other environment where there is a large amount of background noise. The invention utilizes the processing power available in Digital Signal Processor 111 to adaptively adjust the gain of amplifier 202 and filter 205 in the transmit channel to eliminate audio distortion in a “loud talker” environment. The gain correction information is transmitted by the DSP 111 to the digital filter and PCM I/O block 204 in the 3 unused bits of the 16 bit PCM data word thus eliminating any additional connections.