Abstract: A short segment recording and replay system which includes a receiver for receiving and displaying audiovisual information and an endless memory for storage of continuous short segments of the audiovisual information concurrent with display thereof by the receiver. A controller is responsive to a predetermined condition to freeze the contents of the endless memory therein. The endless memory is preferably a addressable random access memory which can be in a plug-in module. The system includes a switching element responsive to the controller for transmitting the contents of the endless memory to the receiver for display. Special effects can be added to the audiovisual information prior to storage thereof in the endless memory or prior to transmitting the contents of the endless memory to the receiver for display.

Abstract: A digital cellular base station (22) having minimum hardware requirements readily adapted to support high speed communication is disclosed herein. It includes a digital signal processor base band processor and modulator (24), a high-speed, high resolution digital-to-analog converter (26), a RF modulator (30) and an antenna (32). An input signal couples to the digital signal base-band processing modulator (24) for processing. The high-speed, high resolution digital-to-analog converter (26) couples to receive the processed signal and converts the signal into an analog one. The high-speed, high resolution digital-to-analog converter (DAC) (26) has off-line sigma delta conversion and storage which enables it to directly generat a modulated signal at an intermediate frequency, typically on the order of 100 MHz. Incorporation of DAC (26) reduces the amount of hardware necessary for the cellular base-station (22).

Abstract: The object of the invention is to provide a power-off detection circuit with low power consumption and little dependence on power supply voltage. Detecting capacitor 11 is charged by the power supply voltage Vcc. When the power supply voltage Vcc drops at the time of power off, the drop is detected by starting transistor 14. Said detecting transistor 11 is discharged, and the discharge current is supplied to gate voltage generating circuit 21. Gate voltage generating circuit 21 generates a gate voltage depending on the discharge current. As a result, output transistor 17 is turned on, and the signal at control terminal 35 is inverted. Another circuit can detect the power-off state depending on the signal at control terminal 35.

Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

Abstract: A yield and failure analysis system having composite wafermaps provides the ability to view numerous lots on a single screen, identifying the semiconductor manufacturing process, which caused wafer failures and the associated malfunctioning equipment. A wafer inspection instrumentation (28) probes each wafer within a given lot and applies a series of tests. Wafer defect data is stored in a first relational database (46) for compiling a composite wafermap for each lot. Collected wafer defect data is converted into a FFT signature. Present wafer defect data is compared with stored converted wafer defect data patterns to generate correlation coefficients. When the correlation coefficients are within a predetermined range, the converted wafer defect data pattern is stored in the second relational database (47). Data may be accessed from both databases by a user interface (44), enabling the user to analyze data in real time and generate reports.

Abstract: A six-axis attachment mechanism for aligning a spatial light modulator (106) within a display system. An attachment plate (100) has one or more pins (104) extending therefrom. A socket plate (108) onto which a spatial light modulator (106) is attached slides over the pins (104). The modulator is then positioned to optically align it with the remainder of the display system. As the modulator is held in alignment, a washer (110) is slid onto the pin (104) and is bonded to both the pin (104) and to the socket plate (108). Washers (110) are typically transparent to enable the use of an optically cured adhesive. Glass washers (110) allow ultraviolet radiation to reach the adhesive through the glass washer (110).

Abstract: A software predictive engine is described that provides a tool to analyze the import of defects in the software development process. By providing a prediction of escaping defects, in terms of the normalized sigma measure and the predicted lines of code, together with historical data the impact of defects at the stages of the design can be predicted. As actual defects are measured predicted sigma level can also be predicted. The engine includes generating a defect containment matrix for the historical data and for the current software program being developed.

Abstract: A method and system for digital resolution translation. An input frequency is received, as is a desired output frequency. The desired output frequency is measured directly and compared with the input frequency. The specified output frequency is dynamically adjusted to compensate for variations in the input frequency, while a fixed relationship between the input and output is kept intact. The relationship between the input and output frequencies can be arbitrary, non-integer or integer. The system consists of an execution process (54) and the adjusted output frequency is sent to a system as a sampling signal. The system reset/restart capability allows for a repeatable phase relationship between the output and the input from any given reset point.

Abstract: An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semiconductor property) different to the crystallographic orientation (or other respective property) of the other semiconductor. This arrangement of crystallographic orientations (and other crystallographic/semiconductor properties) can yield reduced unintended electron tunneling or current leakage through the insulator vis a vis a semiconductor device in which such an arrangement is not used. Methods for forming the MOS-type semiconductor devices of the invention are also provided.

Abstract: A method of making semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably said base.

Abstract: A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.

Abstract: A method and apparatus for delivering a fine mist of a lubricant to a micromechanical device. A mixture 402 of a lubricant and a diluent carrier fluid is held in a supply reservoir 404. The mixture is forced through a nebulizer tip 406 to produce a fine aerosol. A particle selector 408 removes large droplets from the aerosol as the aerosol passes. The aerosol travels a distance through a delivery conduit 410 while the diluent carrier fluid evaporates from the nebulized droplets. The evaporation removes the vast majority of the diluent carrier fluid from the droplets, greatly reducing the size of the lubricant droplets. The evaporated aerosol enters a deposition chamber 412 and is deposited on a micromechanical device 414. The micromechanical devices may be lubricated in wafer form, in which case the lubricant aerosol will lubricate an entire wafer of micromechanical devices at one time. One embodiment produces an aerosol having a mean droplet size of less than 10 microns.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor (Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.

Abstract: The present invention includes a circuit which can achieve a 200 nano second write to read time. The present invention eliminates a switch in the RMR measurement circuit.

Abstract: A method and apparatus (10) for securing a fragile wafer (16) to a wafer tape (26) secured taut across a wafer frame (24). A gentle point force (72) is provided by a roller wheel (36) mounted on a rotatable arm (30) to securely adhere the wafer tape (26) to the backside of the wafer (16). Preferably, a spiral pattern (70) is formed by the rotating roller (36) to secure the wafer tape (26) to the wafer (16) to avoid forming air bubbles or creases between the wafer tape and wafer. The method and apparatus is especially suitable for securely adhering fragile wafers to wafer tape that are to be subsequently broken along kerfs.

Abstract: A circuit is designed with a register circuit (70) arranged to store a control word. A voltage-controlled oscillator (73) is coupled to receive the control word (72) and produce a clock signal (76) having a current frequency corresponding to the control word. A phase detector circuit (53) is coupled to receive a reference signal (52) and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector circuit produces a phase signal (58) having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit (69) is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word (71) corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.

Abstract: A combinatorial polynomial multiplier for Galois Field 256 arithmetic utilizes fewer components than an iterative Galois Field 256 arithmetic multiplier and operates 8 times faster. The combinatorial multiplier employs AND and XOR functions and operates in a single clock cycle. It can reduce the number of transistors required for the Galois Field 256 arithmetic multiplier for a Reed-Solomon decoder by almost 90%.

Abstract: The charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop is disclosed herein. It includes a p-type charge pump and a n-type charge pump. The charge pump has inputs for an up and a down voltage output from a phase and frequency detector and for at least two bias voltage outputs from a bias generator. The p-type charge pump is coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit. The n-type charge pump is coupled to the p-type charge pump and has inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit. A first capacitor is coupled across the p-type charge pump. This charge pump operates between 1 &mgr;A to 10 &mgr;A. It is a more balanced design than known charge pump designs.

Abstract: A controller (203) for coupling between a computer bus (20) and one or more units (221, 222) compatible with the bus. The controller comprises a first input (28) for receiving a first reset signal issued from the computer bus, and a second input (30) for receiving a second reset signal. The controller further comprises circuitry (26) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry (24) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.

Abstract: The purpose of this invention is to provide a method for manufacturing capacitors free of polarization fatigue even when the treatment is performed at a low temperature. Amorphous layer 32 made of lead zirconate titanate and containing excess lead is formed on lower electrode 13 made of iridium. The amorphous layer is crystallized by a heat treatment to form PZT film 14. Structural transition layer 33 containing excess Pb formed on the surface of PZT film 14 during the aforementioned crystallization is removed by means of dry etching. In this way, a PZT capacitor is obtained.