Abstract: A microactuator includes a base, first microactuator elements carried by the base, a platform attached to the base, second microactuator elements carried by the platform, and the first microactuator elements being located substantially symmetrically on either side of a plane along a centerline of the base

Abstract: A flexible carrier tape system, suitable for housing components and for winding on a reel in high density, is disclosed, comprising an elongated base strip having a plurality of longitudinally spaced cavities with side walls having a step-like groove near the surface around the cavity, comprising further an elongated cover strip having a width matching the width of the cavity including the widths of the grooves, the cover strip sealed onto the base strip so that the cover strip rests on the step-like grooves. In one embodiment, the sealed cover strip forms a substantially uniform plane with the upper surface of the base strip. The thickness consumed by each tape winding becomes a minimum so that a high density of components can be stored and transported.

Abstract: A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at least one-half of the length of the field oxide layer (20).

Abstract: An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn (104) which clamps to voltage at the pad (110) and dissipated the ESD current. The lateral npn (104) is the primary protection device for dissipating ESD current.

Abstract: An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.

Abstract: The objective of the invention is to provide a booster circuit with reduced power consumption and switching noise. Booster circuit 1 of the present invention has gate circuits 41-47 an auxiliary control circuit 9. Each of gate circuits 41-47 has charging/discharging circuit 11 and auxiliary charging/discharging circuit 12 used for charging/discharging capacitors 51-57. Under the control of auxiliary control circuit 9, said charging/discharging circuit 11 can operate independently or operate together with auxiliary charging/discharging circuit 12. When the booster circuit is started, charging/discharging circuit 11 and auxiliary charging/discharging circuit 12 are operated together to increase the drivability of gate circuits 4. As a result, the charging time of capacitors 51-57 in charge-pump circuits 22-27 can be shortened. On the other hand, at steady state, charging/discharging circuit 11 operates independently.

Abstract: A process of removing fluorine from a chemical deposition reactor includes the step of injecting a gaseous mixture of nitrogen and hydrogen into the reactor, the volume ratio of nitrogen to hydrogen in the gaseous mixture being in the range of from 1:1 to 6:1. More preferably the N2/H2 ratio is in the range of 2.5 to 4.5:1. The gaseous mixture is ionized with a RF induced energy discharge, with a RF power setting typically in the range of from 200 to 250 watts at an RF frequency of 13.5 MHZ. The gaseous mixture is injected into the reactor for a predetermined period of time based upon the thickness of a material, typically a metal such as tungsten, deposited upon a wafer in the reactor during a semiconductor fabrication process.

Abstract: High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Abstract: An automated assembly line is operated and controlled by a computer system. The assembly line includes of a plurality of machines which are each segmented into its basic unit operations providing work stations. The work stations are then controlled by the computer system and operated asynchronously with respect to the other work stations of the assembly line.

Abstract: A carrier and cover tape assemblage for semiconductor devices which maintains integrity through bake temperature of 125 degrees C is provided by cover and carrier tapes of the same material, such as polycarbonate, and thus having the same thermal properties so that the joining adhesive is placed under minimal stress to cause delamination or distortion.

Abstract: A subframe-based correlation method for pitch and voicing is provided by finding the pitch track through a speech frame that minimizes pitch prediction residual energy over the frame. The method scans the range of possible time lags T and computes for each subframe within a given range of T the maximum correlation value and further finds the set of subframe lags to maximize the correlation over all of possible pitch lags.

Abstract: An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Abstract: A digital-to-analog converter is provided for accomplishing analog output characteristics using different digital-to-analog conversion type digital signal processing schemes. A plurality of bits of a received digital signal are divided into a plurality of bit groups. A digital signal processing unit includes a plurality of bit group digital signal processors for receiving the plurality of bit groups. The plurality of digital signal processors employ one or more digital-to-analog conversion type digital signal processing schemes for generating a plurality of digital signal processed outputs. The converter adds the plurality of digital signal processed outputs to generate a composite signal processed output, and includes a weight generating unit for controlling a plurality of shared weight generating elements in response to the composite digital signal processed output to generate an analog output signal.

Abstract: An interface circuit (10) for use in a read channel of mass data storage device and which is synchronous with a clock (CLK8) of the mass data storage device operates to receive data (12) coming into the circuit (10) controlled by an associated controller. The circuit (10) is easily configurable to process either a full word length at once, or by half-word portions. In the half-word mode, the data coming into the circuit is clocked into one of three data registers (18, 36, 38). When a flag (NZH, NZL) that indicates that data is starting is detected, the phase of the received data with respect to the clock is determined by comparing (50) the phase of the full word clock (CLK8) to the phase of a half-word clock (CLK4). If the clocks are in-phase, the first two registers (18,36) are selected to contain respective halves of the data word. If the clocks are out-of-phase, the second two registers (36,38) are selected to contain the respective halves of the data word.

Abstract: A structure and method for fabricating an integrate circuit crown structure for use in a DRAM cell on a substrate comprising a common source/drain region (18) disposed within a substrate (12), the common source/drain region (18) connected to a bitline (22), a gate oxide (28) disposed over the common source/drain region (18) and forming at least two wordline gates (30), at least two storage node source/drains (20) adjacent to said gates (30) and contacted by storage node contacts (38) and a storage node bowl (36), the bowl being formed within adjacent supporting layers formed over said wordline gates wherein the storage node bowl (36) is formed, and electrically isolated from, the bitline (22) without being exposed to etching agents during its formation and without forming a wine glass stem structure and a crown extending from the top of the storage node bowl (36), is disclosed.

Abstract: Speech recognition and the generation of speech recognition models is provided including the generation of unique phonotactic garbage models (15) to identify speech by, for example, English language constraints in addition to noise, silence and other non-speech models (11) and for speech recognition specific word models.

Abstract: For the transfer of data coming from N channels, which are sampled in a pre-determined sequence, to a processor by means of a circular FIFO store (30) with n storage stages, whilst retaining this pre-determined sequence, and whereby the output of the last stage is connected to the input of the first stage, the following steps are implemented: a) With each write operation of data into the FIFO store (30), a write pointer (SZ) is set to a value which designates the storage stage into which has been written last; b) with each reading operation of data from the FIFO store (30), a read pointer (LZ) is set to a value which designates the storage stage which is subsequently to be read, whereby the reading process always comprises the reading of data from i×N storage stages, i being an integer and i×N<n; c) a trigger pointer (TZ) is set to a value j×N, j being an integer, j×N<n and i≦j; d) if, after a write process, the value of the write pointer (SZ) is equal to or greater than t

Abstract: A voltage supply circuit capable of starting up a system while maintaining symmetry of a high level selection signal VH and a low level selection signal VL, not requiring a multistage charge pump circuit, and capable of reducing the number of parts of the system, wherein generation circuits of VD and VH are comprised of chopper type booster type switching regulators, and switching timings of a VH generation circuit 12 and a VL generation circuit 13 are controlled so that a virtual reference voltage VS (VD/2) and a middle point potential between VH and VL become the same.

Abstract: A micromirror device having an array of mirrors 802 formed with a jagged leading 804 and trailing 806 edge. The jagged leading and trailing edges eliminate the features that cause the most diffraction-straight edges that are perpendicular to the incident illumination 808. The leading and trailing edges preferably are formed as a series of saw teeth having a 45° angle to the incident illumination 808. Angling the edges relative to the illumination axis greatly reduces the diffraction that would occur from edges perpendicular to the illumination axis. By reducing the diffraction, the jagged leading and trailing edges enable the use of orthogonal illumination which reduces the cost, size, and weight of the associated TIR prism. The number of saw teeth can vary, but the three-tooth pattern provides an optimum mixture of low diffraction and ease of production.