Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.

Abstract: A method for shuffling capacitors, for application in a stage of a pipelined analog-to-digital converter that samples an input voltage at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input voltage. The stage includes an amplifier and a plurality of capacitors which may be connected between the input voltage and an AC ground at a first time and which may be connected between the output of the amplifier and an input of the amplifier, or which may be connected between the input of the amplifier and one of a plurality of reference voltage sources at a second time. The method includes the following steps. A plurality of coded input values are provided, each such coded value corresponding to the connection of one of the capacitors between the input of the amplifier and either the at least one voltage sources or the output of the amplifier. A predetermined sequence of control codes is provided.

Abstract: A frame-addressed bistable micromirror array and method of operation. An analog input signal representing the desired intensity of an image pixel is applied to input 302. An address signal synchronized to the analog input signal is applied to input 304 of a given micromirror cell to store the pixel intensity information on input capacitor 306. After intensity information for each pixel in the video frame or field, or a portion of the frame of field, is stored on the input capacitor 306 of the appropriate micromirror cell, a frame signal is applied to input 308 to enable the transfer of charge between capacitors 306 and 310 and to turn on transistor 314 allowing a voltage applied to input 316 to charge capacitor 318. The pre-charge voltage is chosen to ensure the biased micromirrors are fully deflected to a first state. A ramp voltage is applied to input 322. A ramp voltage is applied to input 322.

Abstract: A system 400 and method 1400 are disclosed for a lock detection circuit of a phase locked loop used in a communications device. The lock detection circuit includes a cycle slip detector and a clock presence detector. The cycle slip detector receives a reference clock and a VCO feedback clock, and in response to the frequency difference between the reference clock and the VCO feedback clock that remains for a time period greater than the inverse of the frequency difference of the clocks, generates a no cycle slips alarm indication. The no cycle slips alarm status enables the lock detection circuit to provide an indication to the PLL, of the lock condition and whether a cycle slip has occurred. The clock presence detector receives the reference clock and the VCO feedback clock, and in response to determining whether the reference clock or the VCO feedback clock is missing for a time greater than a predetermined count of either remaining clock, generate a no VCO alarm and a no REF alarm indication.

Abstract: An apparatus for forming a stamped groove in a lead frame including a tool for coining the groove in the lead frame. The tool has a shoulder to control swelling of the lead frame surface near the groove.

Abstract: Apparatus for generating an oscillating signal in a desired phase relationship with an input signal, including a mixer arranged to receive a pair of reference signals oscillating at a common frequency and having a phase offset between them, and to mix the reference signals in variable proportions according to the value of input weighting signals to generate an output signal. A comparator is to compare the phase of the output signal with that of the input signal to determine whether the signals are in the desired phase relationship and, if not, to output one or more control signals indicative of the required adjustment in the phase of the output signal to achieve the desired phase relationship. An adjustable ring oscillator including a plurality of stages is connected in a ring and arranged to propagate oscillations around the ring.

Abstract: A semiconductor chip bearing an alignment mark, particularly useful for wire bonder alignment on chips having bonding surfaces over the active circuits. The marks are fabricated on diagonal corners of the chip, and each mark consists of a pair of touching squares which are rotated about 90 degrees from each other in the opposite chip corners. The unique positioning of the marks, as well as the rotation provides both gross chip position features useful in mounting the chip on a lead frame, as well as fine alignment set-up or teaching aids for wire bonding. The small, high visual contrast features of the alignment mark are fabricated simultaneously with the top active metallization of the IC chip, and are not covered by passivation coating or additional metal layers.

Abstract: A system for driving a signal is provided that includes a biasing circuit operable to receive an input signal and operable to produce a bias signal based on the input signal. A drive circuit includes a sensor circuit including a transistor coupled to a first power supply. The drive circuit is coupled to the biasing circuit. The drive circuit is operable to receive the bias signal and to produce an amplified signal based on the bias signal. An output circuit includes a transistor coupled to a second power supply. The output circuit is coupled to the drive circuit. The output circuit is operable to receive the amplified signal and to produce an output signal based on the amplified signal.

Abstract: The present invention achieves technical advantages as an overshoot circuit (30) for a voltage source/impedance based write coil driver circuit (10) accurately controlling the current (IW)through a coil (LH) that is used to write data to a magnetic medium. The circuit (30) improves the characteristics of the coil.

Abstract: A low voltage low THD CMOS audio power amplifier (60) which can work at lower supply voltage with lower THD is presented. A Class AB input stage (40) is provided that can be used in the extremely low THD circuit (60). Compared to a conventional differential input stages (30), for a given quiescent current consumption, the Class AB input stage (40) achieves a much larger output dynamic current and a higher slew rate. In addition, the input stage (40) achieves a flat signal/distortion versus frequency characteristic. A Class AB output stage (80) has a higher over-drive gate-source voltages for the output transistors and thus has a higher driving capacity as compared to a conventional output stage (70) making it suitable for low voltage CMOS designs operable at supply voltages as low as 1.5 volts.

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the Semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.

Abstract: A low dropout voltage regulator includes: a first amplifier A1 having a reference voltage node VREF coupled to a first input; a second amplifier A2 having an input coupled to an output of the first amplifier A1; a variable bias current source I1 coupled to the first amplifier A1 and having a control node coupled to an output of the second amplifier A2; a power switch M1 having a control node coupled to the output of the second amplifier A2 and having a first end coupled to a source voltage node VDD; and a feedback circuit R1 and R2 having an input coupled to a second end of the power switch M1 and an output coupled to a second input of the first amplifier A1. The best node in the system that detects the load current level is the output of the second amplifier A2. This signal is used to modulate the bias current I1 of the first amplifier A1 by increasing the bias current when the load current increases and vice versa, which consequently modulates the transconductance of amplifier A1.

Abstract: A transconductance circuit having a high output impedance has a dual input differential transconductor (10) with first (14) and second (16) differential inputs and a differential output (18). The first differential input (14) is connected to receive a dc voltage (20). An inverting feedback path is connected between the second differential input (16) and the differential output (18). A differential difference amplifier (24) has a first input (26) connected to receive the dc voltage (20) and a second input (28) connected to the inverting feedback path. A variable resistor (22) is connected across the differential output (18). The output (30) of the differential difference amplifier (24) is connected to control the variable resistor (22) to minimize the output of the differential difference amplifier (24), thereby creating a high output impedance from said transconductor (10).

Abstract: A method for forming a thin aluminum-nitride film (112). Solid hydrazine cyanurate is heated to produce in-situ hydrazine (N2H4). The in-situ hydrazine reacts with a previously deposited ailminum layer (108) to form aluminum-nitride (112).

Abstract: According to one embodiment of the invention, a method of forming an asymmetric I/O transistor includes forming a first oxide layer outwardly from a semiconductor substrate, masking a first portion, less than a whole portion, of an I/O transistor region with a first photoresist layer, removing the first oxide layer from a core transistor region and a second portion of the I/O transistor region, removing the first photoresist layer, forming a second oxide layer outwardly from the substrate, forming gates for the core transistor region and the I/O transistor region, masking the first portion of the I/O transistor region with a second photoresist layer, doping a source region and a drain region of the core transistor region and a source region of the I/O transistor region with a first dopant, doping the source region and the drain region of the core transistor region and the source region of the I/O transistor region with a second dopant, removing the second photoresist layer, masking the core transistor region

Abstract: A technique is described for providing cavities between the conducting paths of an integrated semiconductor circuit. These cavities can have air or a gas trapped therein to decrease the dielectric constant between two conducting paths. After forming the conducting paths, an etchable fill material formed between and over the conducting paths. An oxide cap is formed over the fill material. Conducting plugs, extending through the fill material and the oxide cap, and electrically coupled to the conducting paths are formed. A photo-resist layer applied over the conducting plugs and the oxide cap. The photo-resist layer is structured to permit access to the oxide cap between the conducting plugs. A “pin-hole” is fabricated through the oxide cap and the fill material exposed by the “pin-hole” is etched away. The “pin-hole” is plugged with additional oxide cap material and a surface is then formed on the oxide cap exposing the conducting plugs.

Abstract: An input to a rail-to-rail, FET, operational amplifier having a transconductance that is constant throughout the operating range of the operational amplifier is presented. The input of an operational amplifier typically includes an input stage, a current source and a current transfer circuit, wherein the input stage comprises both N-type transistors and P-type transistors. The present application discloses the use of a duplicate of those elements: a proportional input stage, a proportional current source, and a proportional current transfer circuit, which together are used to emulate the operation of the input stage. By monitoring these proportional duplicates, one can determine when both input pairs are operating. When both input pairs are operating, a minimum selector circuit interfaces with the current transfer circuit to reduce the current supplying one of the input pair transistors, thus reducing the overall transconductance of the circuit.

Abstract: Beam implantation is combined with plasma implantation of oxygen, and possibly also internal thermal oxidation, to form a high quality buried oxide layer.

Abstract: An analyzer and synthesizer (500) for human speech using LPC filtering (530) of an excitation of mixed (508-518-520) voiced pulse train (502) and unvoiced noise (512) with fractional sampling period pitch period determination.