Abstract: Beam implantation is combined with plasma implantation of oxygen, and possibly also internal thermal oxidation, to form a high quality buried oxide layer.

Abstract: A method for effecting a finishing operation on a semiconductor workpiece situated in a finishing apparatus that includes a finishing tool configured for pressingly engaging the workpiece with a pressing force for abradingly removing material from the workpiece includes the steps of: (a) situating the finishing tool to operate against the workpiece; (b) operating the finishing tool with a pressing force to effect the abrading removal; (c) measuring at least one parameter associated with the finishing operation to determine at least one parametric value for the at least one parameter; (d) modulating the pressing force according to a predetermined relationship between the pressing force and the at least one parametric value; and (e) repeating steps (c) and (d) until the finishing operation is complete.

Abstract: A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer (118), a p-type type dopant is implanted to form drain extension regions (126, 122, 124) in the pMOS digital core region (102), pMOS I/O region (104), and the pMOS analog core region (106). Using a second masking layer (132), a n-type dopant is implanted into at least a drain side of the nMOS analog core region (110) and the nMOS I/O region (108) to for drain extension regions (142, 144) and into the pMOS digital core region (102). This forms a pocket region (140) in the pMOS digital core region (102) but not the pMOS analog core region (106) or the pMOS I/O region (104).

Abstract: A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (108) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern (120) is formed and both the via protect layer (114) and IMD (108) are etched. The remaining portions of the via protect layer (114) are then removed prior to forming the metal layer (122).

Abstract: A structure is designed with a lightly doped substrate (316) having a first conductivity type and a face. A first lightly doped region (314) has a second conductivity type and is formed within the lightly doped substrate. A first heavily doped region (308) has the first conductivity type and is formed at the face and extends to a first depth within the first lightly doped region. A second heavily doped region (312) has the second conductivity type and is formed at the face abutting the first heavily doped region. The second heavily doped region extends to a second depth and is at least partly within the first lightly doped region. A first isolation region (304) is formed at the face, abutting at least one of the first and second heavily doped regions. The first isolation region extends to a third depth that is greater than either of the first and the second depths.

Abstract: A capacitor (100) with a high dielectric constant oxide dielectric (102) plus Ir- or Ir and Rh bond over the oxygen site in Barium strontium titanate (BST) dielectric to achieve the high Schottky barrier, and very thin layers of Ir or Rh with conductive oxide backing layers (106, 116) provide oxygen depletion deterrence. Rh-containing capacitor plates (104, 114) yielding high Schottky barrier interfaces.

Abstract: A cleaning agent for use in the manufacture of a semiconductor device comprising an aqueous solution containing a quarternary ammonium salt and a fluoro compound, or an aqueous solution containing a quarternary ammonium salt and a fluoro compound, as well as an organic solvent selected from the group consisting of amides, lactones, nitriles, alcohols and esters. In the semiconductor device manufacturing process, after forming a mask with a photoresist, a wiring structure is formed by dry etching of a conductive layer, wherein a protecting deposition film has been formed on side walls of the conductive layer. Use of the cleaning agent enables the protecting deposition film to be removed in a highly reliable manner with the surface of the conductive layer being decontaminated and cleaned such that no corrosion of the conductive layer occurs.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: A color comb filter (46), video decoder (40) and method for separating chroma (U,V) and luma (Y) signals from a composite video signal (41). The comb filter (46) includes circuitry (48) for generating color filter selections for filtering a chroma video signal (41) and control logic (62) for determining the filter selections based on color boundary properties of the chroma video signal (U,V). The video decoder (40) includes a comb filter (46), a demodulator (42), low pass filter (44), a remodulator (48) and a subtractor (50). The filtered, remodulated chroma signal (Uout,Vout) is subtracted from the composite video signal (41) to produce a luma signal absent hanging dots and false colors.

Abstract: A method of and system for compressing and transmitting information which comprises recognizing a plurality of different types of information and providing a first representation of a recognized one of the plurality of different types of information having lower bandwidth transmission requirement than the recognized one of the plurality of different types of information. The first representation is transmitted to a remote receiver and a second representation of the recognized one of the recognized one of the plurality of different types of information at said remote receiver having greater information content than the first representation responsive to the first representation is provided. Responsive to the second representation, a recreation of the recognized one of the plurality of different types of information is provided. Recognizing includes providing a first data base and the second representation includes providing a second data base.

Abstract: An oscillator controls the frequency of an output clock signal in response to detecting an error in the frequency of an input clock signal. The oscillator includes an inverter operable to generate a voltage signal and a resonator coupled to the inverter operable to introduce a phase shift in the voltage signal. The oscillator also includes a variable resistor positioned across a feedback path of the inverter and operable to introduce a further phase shift in the voltage signal in response to the detected error. The resonator is further operable to adjust the frequency of the voltage signal in response to the introduced further phase shift. The voltage signal is used as the output clock signal.

Abstract: A spot-implant method for MOS transistors. An asymmetric masking film (50) is formed on a semiconductor substrate and on a transistor gate (30) with an opening (45) adjacent to the transistor gate (30). A spot region (70) is formed adjacent to the transistor gate (30) by ion implantation (60).

Abstract: A self-aligned silicide process with a selective etch of unreacted metal (plus any nitride) with respect to silicide plus a two step process of highly selective strip of unreacted metal (plus any nitride) followed by a silicide etch to remove unwanted silicide filament.

Abstract: A flip-flop (14) is disclosed that includes an input circuit (50), a sense amplifier (52) and an output circuit (56). The input circuit (50) is operable to receive a data input signal and to generate complementary data signals. The sense amplifier (52) is coupled to the input circuit (50). The sense amplifier (52) is operable to receive the data signals from the input circuit (50) and to generate complementary amplified signals based on the data signals. The output circuit (56) is coupled to the sense amplifier (52). The output circuit (56) is operable to receive the amplified signals from the sense amplifier (52) and to generate complementary output signals based on the amplified signals.

Abstract: A class AB input differential amplifier employs a single loop output common mode feedback circuit (CMFC) to achieve high performance by controlling the common mode output voltage. The CMFC includes a small amplifier to compare the common mode voltage at the output with a desired voltage specified at the common mode output voltage pin. Having only one loop to control this voltage instead of two makes the design more reliable and easier to compensate since there is no need to worry about how multiple loops will interact.

Abstract: A regulated integrated circuit power supply (200) intermittently applies feedback to a charge pump (202) on a sampled basis such that a feedback circuit (204) is enabled to sense the bias voltage (Vout) at predetermined intervals of time. Based upon the value of the bias voltage (Vout) as compared to a threshold voltage (VT), the charge pump (202) is enabled to supply a voltage to the integrated circuit. Thereby, the regulated charge pump (202) does not overload the integrated circuit coupled thereto. The regulated integrated circuit power supply (200) includes the charge pump (202) coupled to the integrated circuit to supply bias voltage (Vout). Additionally, coupled to the integrated circuit, the feedback circuit (204) senses the bias voltage (Vout) and provides an output signal based upon a comparison between the bias voltage (Vout) and a voltage threshold (VT) A switch (208) connected to the feedback circuit (204) selectively enables and disables sensing of the bias voltage (Vout).

Abstract: A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.

Abstract: A method of manufacturing a ball grid array semiconductor package includes the step of providing a substrate (103) having a first surface (103b) and a second surface (103a), in which the first surface (103b) or the second surface (103a) include a conductor pattern (104). The method also includes the step of disposing a plurality of conductive bumps (107) on the first surface (103b) of the substrate (103) and attaching a semiconductor die (102) to the second surface (103a) of the substrate (103). The method further includes the step of electrically connecting the conductive bumps (107) to the conductor pattern (104), such that electrically connecting the conductive bumps (107) to the conductor pattern (104) mechanically affixes the conductive bumps (107) to the first surface (103b) of the substrate (103).

Abstract: A leadframe structure for use with an integrated circuit chip, comprising a chip mount pad having an area smaller than said chip intended for mounting; a plurality of support members, each attached externally to the perimeter of said pad and internally to said leadframe; and each said support member having at least one portion located within the perimeter of said chip in a configuration operable to absorb thermally induced deformations of said support member.

Abstract: A “multi-stage” method of estimating pitch in a speech encoder (FIG. 2). In a first stage of the method, a set of candidate pitch values is selected, such as by using a cost function that operates on said speech signal (steps 21-23). In a second stage of the method, a best candidate is selected. Specifically, in the second stage, pitch values calculated from previous speech segments are used to calculate an average pitch value (step 25). Then, depending on whether the average pitch value is short or long, one of two different analysis-by-synthesis (ABS) processes is then repeated for each candidate, such that for each iteration, a synthesized signal is derived from that pitch candidate and compared to a reference signal to provide an error value. A time domain ABS process is used if the average pitch is short (step 27), whereas a frequency domain ABS process is used if the average pitch is long (step 28).