Abstract: A rotation device provides precise, stepwise rotation of a wire bonding capillary about the longitudinal axis of the capillary. This enables the capillary to be rotated to different angular alignments to perform wire bonding in different directions. The rotation device can be a click ring-type device, a cam-type device or any other device to provide stepwise rotation. At least a part of the rotation device is coupled to the capillary. Another part of the rotation device is separate from the capillary but engageable with the first part to provide rotation. Indicators may be positioned on the capillary to provide signals to detectors. The signals can be used to initially align the capillary and to realign the capillary during wire bonding. A computer may be used to provide automated control of the indicators and detectors, and automated rotation of the rotation device.

Abstract: The described embodiments of the present invention provide a computer docking station having connection means for coupling to an external monitor and an external keyboard, means for connecting the portable computer to the docking station, and at least one PCMCIA option card slot in the docking station. In a preferred embodiment, the computer docking station further includes a controller in the docking station to provide the necessary hardware interface between the PCMCIA cart slot and the portable computer and software means for providing the necessary driver support.

Abstract: A system and method for detecting battery removal or absent battery condition in a charger without use of external stimulus such as a thermistor, EEPROM, or additional pin. The system and method use information solely available from the charger positive and negative terminals to correctly annunciate the current state of the charger to a host or end-user.

Abstract: A method and apparatus for manipulating data from a processor on a stack memory is disclosed. The method and apparatus comprises aligning a stack pointer (104) in the stack memory (110) to a first memory address (126). The method further comprises incrementing the stack pointer (104) to a second memory address (128). The method further comprises saving data from a register (102) into the stack memory (110) at the second memory address (128). The method further comprises aligning the stack pointer (104) to a next even address if at an odd address when the saving step is complete. The method further comprises performing processor operations. The method further comprises unaligning the stack pointer (104) from the even address back to the odd address. The method further comprises restoring data from the stack memory (110) into the register (102). The method further comprises decrementing the stack pointer (104) from the second memory address (128) to the first memory address (126).

Abstract: Providing facsimile communications in a system wherein an originating facsimile terminal equipment (FTE) connects to an intermediate digital network of unknown and unpredictable delay via an originating facsimile interface unit (FIU) and wherein a destination FTE connects to the network via a destination FIU. The originating FTE sends data to the destination FTE via the originating FIU. The originating FIU sends the data to the destination FIU. While the destination FIU is waiting for data from the originating FTE, the destination FIU sends made-up data to the destination FTE to prevent protocol timeouts of the destination FTE. The FTEs operate under the G3 protocol. The made up data is either fill data or stall data, depending on the amount of data accumulated at the destination FIU and on the types of network delays.

Abstract: A stacked multichip assemblage including a plurality of integrated circuit die directly attached to a substrate having pads corresponding to terminals on the die, and interconnections between the die, and also to external contacts. The stacked integrated circuit arrangement includes a first chip(s) having an array of bumped terminals positioned on the corresponding pads of the substrate, a larger integrated circuit chip having perimeter bump terminals located over the first chip, and the terminals directly bonded to corresponding pads on the substrate.

Abstract: A mass production process for semiconductor circuits and modules using a combination of thin film platinum metallization dielectric masking, and three-dimensional laser ablation, in conjunction with a solder combinations and melting temperatures. These combinations have been employed for the fabrication of silicon chips as well as connective substrates. Furthermore, spacing films with adhesive properties on both surfaces have been successfully used for assembling multi-chip cubes.

Abstract: A bump connection structure and a method of attachment to integrated circuits or packages is provided which comprises a prefabricated core structure coated with solderable metal layers to form a composite bump. Said composite bump is aligned to contact pads of the chip or package which have been coated with solder paste, and the assembly heated to form a metallurgical bond. The prefabricated core structures are comprised of metal, plastic or ceramic of the size and dictated by package standards. The connection structure is preferably lead free.

Abstract: A method for efficient interleaving of variable-length packets is provided. In packet networks, block interleaving of variable-length packets can be inefficient when the interleaver block size is fixed and smaller than the packet size. For certain packet lengths, the remaining number of elements for the last block (i.e., bytes or symbols) can be very low. The present invention provides a way to calculate the optimal interleaver block sizes for a preselected packet length and a preselected interleaver width.

Abstract: A monolithic, low power, digital-to-analog converter (DAC) circuit which uses an efficient transistor element to perform both switching and resistive current division functions simultaneously. This allows a R-2R type ladder network to be built using only conventional MOS transistors which can both switch and accurately divide current among the branches of the ladder network, without the need for separate resistors. The lower parts count and requirement for MOS transistors only, without the need for separate resistors, makes this circuit very compatible with low cost monolithic implementation. The DAC of this patent is useful in an application requiring the multiplication of two analog signals, where one of the signals is presented as a digital word. In this application, a Gilbert multiplier circuit is used to multiply the two signals, Vdig and Vsig, where Vdig represents the binary-weighted discrete levels from the DAC and Vsig is a continuous analog signal.

Abstract: A multiple cycle memory access unit issues a memory access load or store, delaying a predetermined number of instruction cycles between it activation and its initial data transfer. The multiple cycle memory access unit controls a predetermined plural number of accesses and operates independently and in parallel with the instruction flow of the data processor. The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay. The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers.

Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.

Abstract: A computer system and method provides a user the ability to restore operation to a previous state from a non-volatile semiconductor memory. The computer system includes flash EEPROM (electrically erasable programmable read only memory) or another non-volatile semiconductor memory for storing hardware configuration and other state information prior to a system power-down. The configuration information is used at power up to reconfigure devices coupled to the processor, such as a hard disk drive controller, video controller, sound card, and so on. Remaining memory in the computer system can be restored either from a hard disk drive (or other mass storage device), or from flash memory. The flash memory may be combined with fast semiconductor memory, such as dynamic random access memory (DRAM) in a module, such that the necessary amount of non-volatile memory may be added whenever fast semiconductor memory is added.

Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less then 25 Å thick, preferably one or two monolayers of SiC.

Abstract: A method of minimizing the volume of the depressions 240 in aluminum cavity filling processes, by-depositing a conformal first layer of aluminum alloy 220 by chemical vapor deposition, long-throw sputtering, collimated sputtering, or ionized physical vapor deposition, to partially fill the cavity 202. This layer is preferably deposited at low temperature (eg. less than 300 degrees C.) and lower deposition pressure (if deposited by sputtering). Subsequently, a second layer of aluminum alloy 230 is deposited by sputtering at temperatures greater than 350 degrees C. and at high power (e.g. greater than 10 kW) to close the mouth of cavity 202. The second layer of aluminum 230 is then forced into the remaining volume of the cavity 202. As part of the cavity 202 is filled with aluminum, alloy 220 before the high pressure aluminum extrusion/reflow, less material is required to be transported into the cavity 202. Therefore, a smaller depression 240 above the cavity is produced.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 M Pa, and preferably no more than about 30 M Pa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: A low drop-out (“LDO”) voltage regulator includes an output stage of having a pass device and a discharge device arranged in complementary voltage follower configurations to both source load current to and sink load current from a regulated output voltage conductor. The pass device and the discharge device are controlled through a single feedback loop.