Abstract: A data and communication system including a hand-held unit (17) and an infrared communication satellite (10) is used to provide for the interchange of data between a host computer (13), individual personal computers (15), the hand-held computing unit (17) and factory machinery, including process controllers.

Abstract: A computer uses an environmental manager (20) to detect and respond to changing environmental conditions, in order to enhance and simplify a users interaction with the computer. Environment changes are detected by a plurality of informants (22), each of which has a specified function. Informants communicate through a CIM (26). The CIM (26) establishes communication channels with each informant regarding which information will be provided by the informant and which information that informant needs from other informants. Informants (22) may receive environmental information from a number of sources, including physical location detectors, hardware configurations, software configurations, and network connections. As environmental conditions change, the informants and applications may respond to the changes. A particular capability to respond is the autolaunch capability which detects user behavior and uses this knowledge to automatically load a program responsive to changing environmental conditions.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the device. The device fabrication is then completed.

Abstract: Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.

Abstract: A twisted bit line structure (69) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces (70-73) on an integrated circuit substrate using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit lines trace segments (70, 70′; 71, 71′; 72, 72′; 73, 73′) with discontinuous regions between segments of each trace along a path substantially perpendicular to the bit line traces. Thus, each “phase &pgr;” bit line trace is adjacent a “phase 0” bit line trace along two perpendicular axes.

Abstract: A semiconductor wafer has integrated circuit dies formed in an array of rows and columns. Selector circuits occur in the areas between the dies and are electrically connected to the individual dies for selecting between a functional mode and a bypass mode for testing. Probe areas are formed on the periphery of the wafer for accepting probe pins without contacting the bond pads of the dies. The dies and selector circuits are electrically connected to the probe areas for conducting electrical testing of the dies. The testing occurs by selecting only one die in a particular row and column and maintaining the remaining dies in a standby mode.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming the gate structure over the substrate (step 102 of FIG.

Abstract: A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total thickness of the dielectric stack (60) between the silicon substrate and the top of the dielectric stack just prior to the formation of the thin film resistor (80). Then, the thickness of the dielectric stack (60) is adjusted (60+70) to be an odd integer number of laser quarter wavelengths. The thin film resistor (60) is then formed and overlying dielectric (120) is deposited. The thickness of the overlying dielectric (120) may likewise be adjusted (120+130) to be an odd integer number of laser quarter wavelengths.

Abstract: A termination circuit to reduce the overshoot and undershoot that are generated when switching the voltage level of a transmission line. The terminating circuit (11) has a termination switching circuit (40) and an auxiliary switching circuit (41). When the voltage level of the termination (5) of the transmission line (4) is switched from a low level to a high level, the termination switching circuit (40) switches the termination (5) that is connected to the ground potential at a low level to the power supply voltage (Vcc) corresponding to a high level, but before that connection is completed, due to the fact that the auxiliary switching circuit (41) temporarily connects the termination (5) to the ground potential corresponding to a low level, the impedance of the terminating circuit (11) is temporarily lowered. Therefore, the overshoot and the undershoot that were generated in the past when switching the voltage level can be reduced.

Abstract: A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: A miniaturized integrated sensor (50) useful for indicating the presence of a sample analyte is disclosed. The sensor (50) has a platform (52) with an upper surface (53) and a detector (62), light source (60), waveguide (58), and reflective fixtures (60,62) embedded in the platform (52). The light source (60) is preferably a light emitting diode and sits in a cup-shaped dimple (68) that directs light from the light source (60) toward one of the reflective fixtures (64) to uniformly distribute light across the waveguide (58). The waveguide (58) is coupled to an upper surface (53) of the sensor platform (52) and is coated with a thin film of indicator chemistry (70) which interacts with the sample analyte to produce optic signal changes that are measurable by the detector (62). A lead frame (51) in the platform (52) has pins (54, 55, 56) which provide the interface to the outside world.

Abstract: A linear transform system (18) for decoding video data is provided. The system (18) includes inputs (50, 52, 54, 56, 58, 60, 62, 64) connected in series to a circuit (40) for implementing a decoding algorithm that includes a multiplication circuit stage (42, 44, 46) having a multiple output scaler structure (82, 84, 86). A bit-serial operator stage (48) is connected in series with the multiplication circuit stage (42, 44, 46). The bit-serial operator stage (48) is coupled to a plurality of outputs (66, 68, 70, 72, 74, 76, 78, 80) that generate decoded video data.

Abstract: A method and apparatus for dithering idle channel tones in delta-sigma converters is provided. In a delta-sigma modulator (10), random dither signal (23) is added before quantizing a signal in order to attenuate the idle channel tones. A random number generator (50) coupled to a digital-to-analog converter (52) with an applied biasing current (54) produces the dither signal (23). The dither signal (23) combines with an input signal at the input of a quantizer (14) in order to randomly change the quantizer output (15) and attenuate idle channel tones.

Abstract: A circuit (100) for measuring circuit time delay of an integrated circuit herein provides the ability to accurately measure access time of a memory device (202) without requiring a high performance expensive tester. The apparatus (100) includes a phase detector (108) having a first and a second input (CLK1, CLK2). Both the first input (CLK1) of the phase detector (108) and the input of the memory device (202) are coupled to receive a clocking signal, having a period, T. The second input (CLK1) of the phase detector (108) is coupled to the output of the memory device (202). The two outputs (UP, DOWN) of the phase detector (108) couple to a first and a second filter (110, 114, 112, 116). A comparator is coupled to receive the two filtered outputs for sensing the difference, VDiff, between the two signals. A processing unit is connected to the comparator to calculate the access time, where access time= (VDiff/VDD) T and VDD is the power supply rail voltage.

Abstract: A method of implementing a geometry per wedge (GPW) based headerless solution in a disk drive formatter having a corresponding memory buffer. The disk drive formatter includes high and low processing engines and formats a data storage disk. The method includes the step of processing a command instruction, which instructs the high-level processing engine to execute a disk operation with respect to a predetermined sector. The method also includes the steps of searching for the predetermined sector using sector layout information derived from a GPW table including entries which define the relative position of sector pulses on a track within a data wedge of the disk, and transferring the predetermined sector from the disk to the buffer memory.

Abstract: A step-up DC voltage converters circuit and method of operation which overcomes the problems associated with the prior art skip mode converters by reversing the flow of energy in the step-up DC voltage converter at the end of each switching cycle for a short constant time duration, thus making it possible to operate the step-up DC voltage converter over the full load current range at a fixed frequency which substantially facilitates filtering the output voltage. In addition to this the peak-to-peak output voltage ripple is less as compared to that of skip mode converters.

Abstract: Disclosed is a sensing system and method utilizing a sensor cartridge (10) for making analytical measurements regarding one or more samples (50) of interest, the cartridge (10) comprising an opaque housing (12) having an opening (32), the opening (32) allowing access to one or more electrically conductive contacts (34) and one or more fluidic connectors (36) disposed within the housing (12) and mechanically aligned to the electrically conductive contacts (34), a flow cell (56) having one or more channels connected to the one or more fluidic connectors (36), and a fixed optic sensor (68, 58, 72, 74) disposed within said housing (12) and aligned to a sensing surface on the flow cell. The fixed optic sensor may be, for example, a surface plasmon resonance sensor, a critical angle sensor, or a fluorescence-based sensor. In one embodiment of the present invention, the one or more electrically conductive contacts (32) comprise card-edge contacts (34).

Abstract: The invention disclosed herein is a device and method in which a heat sink (22) is attached to support leads (18) of a leadframe (10) via a welding or mechanical joining technique. The method is performed prior to semiconductor device packaging and is usually performed after the leadframe is etched or stamped, and before it is cut into strips.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.