Abstract: A processor (16) is disclosed that has real-time execution control for debug functions. The processor (16) includes processor circuitry operable to execute embedded code (19) where the embedded code includes background code and foreground code. The processor (16) also includes debug circuitry interfacing with the processor circuitry and operable to communicate with a debug host (12). The debug circuitry is operable to receive a debug halt command from the debug host (12). After receipt of the debug halt command, the processor circuitry is operable to suspend execution of the embedded code (19) to allow debug of the embedded code (19). The processor circuitry is further operable, while execution of the embedded code (19) is suspended, to respond to an enabled interrupt by executing foreground code associated with the enabled interrupt.

Abstract: A socket (10) includes an adaptor (28) which has a seating surface (28b) for an IC (100) and which has a plurality of contact member receiving holes (28d) in the seating surface. The tips (14c) of a plurality of contact members (14) are received through the contact member receiving holes (28d) of the adaptor, with contact established with each respective terminal (101) of the IC (100) that has been placed on the seating surface. The IC on the seating surface is held by means of rotary latches (22). The latches (22) have an opened position for placement of the IC on the seating surface of the adaptor and a closed position for holding the IC from above it, rotating about a shaft (32) fixed to the base. A cover (20) is movable between first and second positions and a links (24) connected to the cover (24) open the latches when the cover is at a first position and close the latches when the cover is at a second position.

Abstract: A method of calculating yield limits for a factory to process semiconductor wafers, including the steps of generating a wafer map from the semiconductor wafers, eliminating die on said wafer map from consideration that have multiple defects, calculating killer probability for each of said die having only one defect, and predicting yield limits from said killer probabilities.

Abstract: A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

Abstract: A method and display system for using the light (110) passing through the spokes of a color wheel (100). The light is a mixed and rapidly changing color. Adding all of the spoke times produces white, but adding a subset creates color artifacts. The spoke times cannot all be added at the same time without altering the white point of the display. The spoke times are added in a sequence and the sequence is altered over time for the same pixel such that the pixel converges to white over time. The pattern of spoke bits is arranged so that as adjacent spoke bit pixels are added, the net spoke light converges to white. The patterns are also varied so that as more and more spoke bit periods are turned on, the net spoke light converges to white. Each spoke bit period adds n-LSBs of white light intensity, so as each spoke bit period is added, n−1 LSBs of white light are subtracted from the white data.

Abstract: A method and circuit are presented for operating a polyphase dc motor in which drive voltages are applied to the windings of the motor in predetermined phases. Zero crossings of currents flowing in respective windings of the motor are detected, and phases of the drive voltages are adjusted to have zero crossings substantially simultaneously with the detected zero crossings of the currents flowing in respective windings of the motor. The method includes generating a set of three waveforms (45,46,47) to provide drive voltages to respective windings of the motor. Each waveform has a period of 360° with a first segment (43) having a value of zero for 120°, followed by a second segment (50) having an “up slope” shape for 60°, followed by a third segment (67,68) having two consecutive “cap” shapes for 120°, followed by a fourth segment (52) having “down slope” shape for 60°. Each waveform of said set is displaced from one another by 120°.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate which includes a dielectric layer formed between a first structure and a second structure, the method comprising the steps of: growing an oxide-containing layer (layer 204 of FIGS. 2a-2d) on the first structure (substrate 202 of FIGS. 2a-2d); forming a silicon-containing layer (layer 206 of FIG. 2b) on the oxide-containing layer; oxidizing substantially all of the silicon-containing layer by subjecting it to an ambient comprised of oxygen and nitrogen with a substrate temperature around 700 to 800 C.; and forming the second structure (layer 214 of FIG. 2d) on the oxidized silicon-containing layer. Preferably, the step of oxidizing substantially all of the silicon-containing layer is performed by subjecting the silicon-containing layer to an ambient containing: N2O with a wafer temperature around 700 to 800 C.; or NO with a wafer temperature around 700 to 800 C.

Abstract: A road vehicle keyless entry system (10) having an in-vehicle communication processor (11) and a remote transponder (15) is provided. The communication processor (10) has a radio frequency receiver (12), a low frequency transmitter/receiver (13) and a controller (14) capable of encrypting and reading the signals sent and received by the low frequency transmitter/receiver (13). The transponder (15) has a radio frequency transmitter (16) that transmits a signal to the communication processor (11) upon receipt of a manual stimulus and a low frequency transmitter/receiver (17) capable of reading and responding to encrypted signals received from the communication processor (11).

Abstract: A circuit 100, which can be used to perform a sample and hold function, includes a switch 112 with a current patch coupled between an input node VIN and an output node VOUT. A capacitor 114 is coupled to the output node VOUT. A replica device 160 includes a current path coupled between the input node VIN and a supply voltage node VDD. A bootstrap circuit, e.g., including a bootstrap capacitor 164, is coupled between a control terminal of the first switch 112 and a control terminal of the replica device 160.

Abstract: The present invention provides for joint estimation of data clock and frame timing in, for example, an M-ary phase-shift-keying (MPSK) signaling scheme with raised-cosine (RC) baseband pulse shaping. Asynchronous samples of the MPSK signal are obtained at a sampling rate greater than the Nyquist rate. A Fast Fourier Transform (FFT) processor processes the acquired samples, and the outcome is passed on to an absolute-value device followed by a peak detector. The present invention then operates to extract clock and frame information from the MPSK signal using a dotting pattern. In addition to clock recovery, the present invention provides for frame synchronization using the dotting pattern. The present invention thus eliminates the need for a long unique work (UW) frame synchronization pattern often included in the preamble of, for example, a time-division multiple-access (TDMA) signal to establish frame synchronization.

Abstract: A high-yield micromirror device and fabrication method. Address electrodes (310) and a separate mirror bias/reset conductor (312) are disposed on a substrate (304). A micromirror superstructure including torsion beam support posts (116), torsion beam hinges (120), a torsion beam yoke (114), a mirror support post (326), and a mirror (102) is fabricated above, and electrically connected to, the mirror bias/reset conductor (312) such that the torsion beam yoke (114) and mirror (102) are suspended above the address electrodes (310). A dielectric layer (328) is formed over the address electrodes (310). The dielectric layer (328), coupled with the elimination of upper address electrodes used in the prior art electrically insulates the address electrodes (310) from contact with the mirror superstructure and prevents conductive debris from shorting either the mirror superstructure or mirror bias/reset conductor (312) to the address electrodes (310).

Abstract: An integrated circuit chip package is provided which incorporates one or more differential pairs of signal lines coupled to an integrated circuit chip. The differential pairs each include a first signal line and a second signal line. The first signal lines are non-coplanar with the second signal lines. The first signal lines of the differential pairs may be provided in a first plane. The second signal lines of the differential pairs may be provided in a second plane different from the first plane. A first ground plane is provided adjacent the first signal lines and a second ground plane is provided adjacent the second signal lines. The spacing of respective signal lines provides, among other things, the capability of having a greater density of differential pairs of signal lines within the planar area of an integrated circuit chip package.

Abstract: A method for bonding includes positioning a bonding strip adjacent a sole first bond head, the bonding strip having a plurality of strip units, and bonding, with only the first bond head, a first number of the plurality of strip units. The method further includes transporting the bonding strip from the first bond head and positioning the bonding strip adjacent a sole second bond head, and bonding, with only the second bond head, a remaining number of the plurality of strip units on the bonding strip. In one embodiment, the method also includes heating at least one of the plurality of strip units prior to bonding the bonding strip. In one embodiment, the method also includes clamping, with a sole clamp, the bonding strip, thereby limiting warpage of the bonding strip.

Abstract: A new liner structure and method to incorporate this liner into process flows in order to lower the processing temperature of aluminum extrusion or reflow cavity filling. The structures produced by this innovative method are particularly useful for advanced sub-quarter micron multi-level interconnect applications.

Abstract: Method and system of interconnecting conductive elements includes forming a lower conductive element (14) having a lower contact section (22) with a width (24) not more than substantially that of an adjacent section (26) of the lower conductive element (14). A first insulation layer (18) may be formed outwardly of the lower conductive element (14). An upper conductive element (16) may be formed outwardly of the first insulation layer (18). The upper conductive element (16) may have a upper contact section (28) with a width (30) not more than substantially that of an adjacent section (32) of the upper conductive element (16). A second insulation layer (20) may be formed outwardly of the first insulation layer (18) and the upper conductive element (16). A contact hold (40) may be formed in the first and second insulation layers (18, 20) exposing a lower contact area (42) of the lower contact section (22) and an upper contact area (44) of the upper contact section (28).

Abstract: The object of the invention is to realize an MR amplifier circuit that is operable with a single power supply voltage, and in which the CMRR can be maintained large. Current supply circuit (10) supplies a prescribed current (IB) to MR element (20) in response to a control signal (SD), the current of resistive element (R2) that is connected between node (ND2) and ground potential is set by means of the equivalent current circuit (40), the current that flows in resistive element (R2) is controlled in response to potential changes of node (ND2) when a noise is applied to MR element (20), and current changes of MR element (20) are suppressed.

Abstract: A processor structure and method of operation are disclosed that comprise a user-configurable on-chip program memory system. The memory system comprises an on-chip memory 31 and a program memory controller 30 that reconfigures memory 31 in response to control values that may be modified by CPU core 20 under program control. In one mode, memory 31 may be mapped into internal address space. In other modes, memory 31 may be configured as an on-chip cache. In conjunction with the cache configuration, the program memory controller may comprise a tag RAM that is initialized upon a transition to cache mode. Program memory controller 30 handles memory mode transitions and data requests; CPU core 20 preferably requests stored instructions from controller 30 in a uniform fashion regardless of memory mode.

Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) having a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.

Abstract: A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions.

Abstract: A television system (10) with interlaced to progressive scan conversion. The system receives interlaced television signals then converts them to progressively scanned data using either field differencing, enhanced field differencing, frame differencing or other temporal processing depending upon which implementation is used. The implementations used depend upon which configuration of the system (10) was purchased, and can be changed with an upgrade to the more expensive implementations.