Abstract: The invention relates to a flexible and cost-effective method for fabricating customized rerouting metallization of the circuit contact pads. Localized depositions of insulating as well as conducting paths are provided with the capability for manufacturing multi-layered networks of interconnection. In a gas-filled chamber, either a focused laser, or an unfocussed lased impinging through a mask, is used to locally heat selected areas of the chip surface. The gas decomposes on the heated areas, depositing insulating or conducting material precisely on the heated surface areas, respectively. With this additional flexibility for product design and assembly, a number of interesting new products can now be fabricated which are in demand in both commercial and military markets.

Abstract: An equalization technique for an ADSL data communications system is disclosed. The effective channel overall response is made a window of length I equal to the length of the cyclic prefix. The response energy output of filtering is monitored against a preset threshold value to adaptively position the window.

Abstract: This pertains generally to precursors and deposition methods suited to aerogel thin film fabrication of nanoporous dielectrics. An aerogel precursor sol is disclosed. This aerogel precursor sol contains a metal alkoxide (such as TEOS) and a solvent, but no gelation catalyst. By a method according to the present invention, such a precursor sol is applied as a nongelling thin film 14 to a semiconductor substrate 10. This substrate may contain patterned conductors 12, gaps 13, or other structures. An independent gelation catalyst (preferably, vapor phase ammonia) is added to promote rapid gelation of the thin film sol 14 at the desired time. One advantage is that it allows substantially independent control of gelation and pore fluid evaporation. This independent catalyst introduction allows additional processing steps to be performed between sol deposition and the onset of substantial gelation. One potential step is to evaporate a portion of the pore fluid solvent.

Abstract: A phase-locked loop circuit is disclosed. The phase-locked loop circuit includes a fundamental/quadrature phase comparator circuit (12) that compares an input bitstream (IN) to fundamental and quadrature phases of an output clock signal (CLK, CLKQ), to generate logic signals (I1, I2) corresponding to the state of the output clock signal phases at the time of each transition of the input bitstream. Compare logic (44) in the fundamental/quadrature phase comparator circuit (12) generates anticlockwise (A) and clockwise (C) signals to a state machine (14), in response to the logic signals (I1, I2) varying from a prior state (X1, X2) in opposing directions in a sequence; the sequence and directions are indicative of the polarity of the error frequency between the input bitstream and the output clock signal.

Abstract: A method for generating a synchronous clock signal and a circuit (10) for implementing the method described. To generate the positive-going transition of the clock signal, the method generates a synchronization pulse train using a synchronization signal input. The method generates a second pulse train, having pulses offset in time from and later than those of the synchronization pulse train, to generate the negative-going transition of the clock signal. Because there is little loss in duty cycle, when the synchronous clock signal is input to a power factor correction (“PFC”) and pulse width modulation (“PWM”) controller circuit, the PFC and PWM controller is able to operate normally.

Abstract: A charge pump (10) includes a supply voltage terminal (16) and a ground terminal (18) for generating at an output terminal an output voltage (34) which is higher than the voltage present at the supply voltage terminal. It has two complementary MOS field-effect transistors (12, 14), the source-drain paths of which are connected in series between the supply voltage terminal and the ground terminal. It further has a driving circuit (26) for driving the two MOS field-effect transistors and a charge storage capacitor connected by one terminal to the point connecting the source-drain paths of the two MOS field-effect transistors. This charge storage capacitor is formed by the gate capacitance of a further MOS field-effect transistor (20), the source-drain path of which is connected at one end via a first diode (22) to the supply voltage terminal and at the other end via a second diode (24) to the output terminal.

Abstract: A power supply pulse width modulation (PWM) control system uses peak current program mode (CPM) control for large duty ratios with a smooth transition to voltage mode control at small duty ratios down to zero duty ratio. The PWM control system implements the latch function in an analog, circuit in contrast with commonly employed digital solutions, further resulting in low delay times since it does not have logic and set-up delays that are associated with latches.

Abstract: According to one embodiment of the invention, a method of moving a device from a first position to a second position by an actuation system includes moving the device in response to providing a control signal having a first amplitude for a first time period. The method also includes, immediately after the first time period, moving the device in response to providing a control signal having a second amplitude for a second time period, the device having a nonzero velocity after the second time period. The nonzero velocity has a magnitude that allows the device to coast to, and stop at, the second position after the second time period without receiving a control signal.

Abstract: Lower reflow temperature in dielectrics is obtained by using a composite dielectric film. The composite dielectric film includes a first layer doped in the conventional range. A borophosphosilicate glass (BPSG) thick layer having concentrations of around 4.4 wt. % boron and around 5.6 wt. % phosphorus is exemplary. The composite dielectric film includes a second layer doped excessively. A BPSG thin layer having concentrations between 1-4 wt. % phosphorus and between 7-8 wt. % boron is exemplary. A capping layer of conventional dopant concentration may be additionally added to prevent outdiffusion. A composite dielectric BPSG film can be reflowed around 700° C. as compared to the typical 800-900° C. range. After reflow, etching away the second highly doped layer removes any potential adverse effects.

Abstract: A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans (70) a selected number (68) of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines.

Abstract: An active fail-safe method and apparatus for a LVDS receiver that uses a window comparator circuit to monitor the differential voltage at the receiver's input pins and drive the output to a known logic HIGH state in the absence of a valid input signal; i.e., when the input differential signal is less than a chosen threshold value of approximately 80 mV. Such a condition may occur when the cable is removed or damaged in such a way that no valid input signal is present. In the presence of a valid input signal, the circuit's output tracks the differential input without any degradation to the signal.

Abstract: One aspect of the invention is an integrated circuit (10,110) comprising a digital circuit operable to generate a first signal (21,111) and a driver circuit (20 and 30, 120 and 130) coupled to the signal generating circuit (21,111) and to an output load (40, 140). The driver circuit (20 and 30, 120 and 130) comprises a first transistor (MDA,MODA) operable to sink a first amount of current from an output node (38, 138) when activated and a second transistor (MDC,MODC) operable to sink a second amount of current from the output node (38, 138) when activated. The driver circuit (20 and 30, 120 and 130) also comprises a third transistor (MP1, MP4) coupled to the first transistor (MDA,MODA) and operable to activate the first transistor (MDA,MODA) and the second transistor (MDC,MODC) in response to a transition of a first signal.

Abstract: An interface circuit which can transmit signals at high speed in a back plane application, which, in turn, can transmit signals among multiple circuit substrates via the transmission lines on a back board. Card 52 of the present invention has input circuit 92, wiring 212, and clamping circuit 402. Wiring 212 is connected to the input of input circuit 92, and clamping circuit 402 is connected to wiring 212. A signal is transmitted from transmission line 3 on back board 2 to wiring 212 via socket 42. However, when the transmitted signal rises or drops significantly, the signal is clamped by clamping circuit 402 so that it will not go outside a certain voltage range. The vibration amplitude of the signal becomes small. Consequently, the time needed for the input potential of input circuit 92 to be stabilized can be reduced and signals can be transmitted at high speed.

Abstract: Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.

Abstract: A television receiver (10) that has a spatial light modulator (15) and a projection lens (17a) and that projects images to a screen (18). If the aspect ratio of the image to be displayed does not match that of the spatial light modulator (15), an anamorphic lens (17b) is positioned in the optical path of the image, between the projection lens (17b) and the screen (18). In this case and in typical applications, the spatial light modulator (15) generates an image that is anamorphically squeezed in the horizontal dimension, and the anamorphic lens (17b) widens the image so that the viewer perceives a normal wide-screen image on the screen (18).

Abstract: This invention is a very long instruction word data processor including plural data registers, plural functional units and plural program counters and is selectively operable in either a first or second mode. In the first mode, the data processor executes a single instruction stream. In the second mode, the data processor executes two independent program instruction streams simultaneously. In the second mode the data processor may respond to two instruction streams accessing only corresponding halves of the data registers and function units. Alternatively, the data processor may respond to a first instruction stream including instructions referencing the whole data processor employing A side function units by alternatively dispatching (1) instructions referencing the A side data registers and the A side function units and (2) instructions referencing the B side data registers and the B side function units. In the first mode, the data processor fetches N bits of instructions each cycle.

Abstract: Phonetic modeling includes the steps of forming triphone grammars (11) from phonetic data, training triphone models (13), clustering triphones (14) that are acoustically close together and mapping unclustered triphone grammars into a clustered model (16). The clustering process includes using a decision tree based on the acoustic likelihood and allows sub-model clusters in user-definable units.

Abstract: This invention allows a toll authority to monitor transaction numbers which are sent from a transponder (14) to an interrogator (12). By incrementing the transaction counter stored in the transponder with successful transactions the toll authority can ascertain whether accounting of a transaction has been missed (i.e., a transaction number missing from the sequence), or double-counted (i.e., two transactions with the same transaction number).

Abstract: An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (VDD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (VSS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor.

Abstract: A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Two modes of operation, coarse lock mode and fine lock mode, are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window.