Abstract: A system and method for providing a controllable virtual environment includes a computer (11) with processor and a display coupled to the processor to display 2-D or 3-D virtual environment objects. Speech grammars are stored as attributes of the virtual environment objects. Voice commands are recognized by a speech recognizer (19) and microphone (20) coupled to the processor whereby the voice commands are used to manipulate the virtual environment objects on the display. The system is further made role-dependent whereby the display of virtual environment objects and grammar is dependent on the role of the user.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.

Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.

Abstract: A data processing device uses a portion of a random access memory as an output buffer for holding a frame of PCM sample data which is being output after being processed by a processing unit within the processing device. Fine grained synchronization between a reference clock and a stream of PCM data frames is provided by transferring only a portion of selected frame of PCM sample data PCM(n+1), in response to a time difference 971. A breakpoint address is determined to delineate the portion of the selected frame that is to be transferred. A sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint register is sufficient to monitor addresses as they are provided by an address register for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.

Abstract: A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.

Abstract: An interface for a digital video disk system utilizing a small number of pins which allows a requesting device to initiate data requests and which avoids the phenomenon of lock-up.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A shape modulation transmit loop with digital frequency control permits spectral shaping of a digital pulse stream (12) by controlling the slew rate of the transition signal (16) between successive pulses. The loop is formed when the digital data stream is fed into an up/down counter (152) whose output is coupled to a programmable memory means (154), such as RAM, EEPROM, flash memory or similar electronic storage means. The output (108) of the programmable memory (154) forms a first input to an adder (112) which drives an accumulator (52) with specified steps. Values corresponding to the desired waveform (70) are stored in a lookup table (60) which is coupled to a digital-to-analog conversion circuit (64) which uses the values in the lookup table (60) to construct a sine wave output signal (70) corresponding to the frequency set by the current specified step of the up/down counter (152).

Abstract: In a receiver circuit module (22) having a microcontroller (U1), an output line (FILTER_LED) connectable to a source circuit module (20) is also used as an input. A switch (SW2) disposed in the source circuit module is closed to change the wave form which is read by the microcontroller as an input signal to drive a 5V signal to the gate of a solid state switch (Q1) turning it on to thereby energize an output device in the source circuit module via the same output line (FILTER_LED). By means of the dual function of the output line the control can notify a user of an HVAC system, for example, of system problems with a blinking light and/or an audible alarm as well as serving to notify the user at a remote location that selected maintenance is due, such as a need to change filters without additional control lines. The source circuit module can be mounted near the thermostat of the HVAC system or on the central heating and cooling unit.

Abstract: A system for cleaning a reticle. There is provided a clean chamber and a reticle having a pair of opposing edges and a pair of opposing surfaces which is to be cleaned disposed in the clean chamber. A gas inert to the reticle is directed in a direction tangential to each of the surfaces of the reticle and along one the edge of the reticle. The gas is exhausted from a location spaced from the other of the pair of opposing edges and remote form the one edge. An optional monitor monitors the particles in the exhausted gas. The gas is preferably applied in pulses which have a pulse length of from about 0.05 second to about 1 second and a pulse repetition rate of from about 0.5/second to about 40/second. The gas is preferably ionized and preferably is applied at a pressure of from about 20 psi to about 120 psi. The stepper chamber is vibrationally isolated from the blow-off chamber.

Abstract: A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72). The method involves forming steps (104) in the sidewalls of the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).

Abstract: The invention provides methods and systems for power control in point-to-multipoint communications systems. Methods are described for both downstream and upstream control. Subscriber signals received at the base station 11 are level detected at receiver 77 and power adjust processing 79 and a control signal is sent to control output from the subscriber transmitter 65. The invention maximizes the signal-to-noise ratio and signal-to-interference ratio for subscribers (CPE) while minimizing transmitted power. The invention is ideal for use in local multipoint distribution service (LMDS) systems.

Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.

Abstract: An isolation trench (60) comprising a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A layer (50) of an insulation material may be formed over the barrier layer (22). A high density layer (55) of the insulation material may be formed in the trench (20) over the layer (50).

Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Abstract: A circuit 10 is provided that comprises a source resistance transistor 12 connected to a common node 14. A word line driver circuit 18 receives current if it is the word line driver selected from the VDD supply voltage through the source resistance transistor 12. The gate of source resistance transistor 12 is connected to a bond pad 22 which can be alternatively connected to the VDD supply voltage through a bond pad 24 or to ground potential through a bond pad 26. The effective threshold voltage of a transistor 18 within driver 16 can be adjusted depending upon how the gate of transistor 12 is connected. In this manner, a circuit can be adjusted to compensate for process variation or to be more optimum for a selected application by adjustment of the effective threshold voltage of selected transistors.

Abstract: A conducting path with a path meander provides a precision voltage-dividing circuit. At each location wherein a voltage level is to be established, the conducting path has an expanded region called a junction region. The centers of all junction regions are equidistant from the centers of neighboring junction regions. Junction regions are positioned at predetermined intervals along the straight portions of the conducting path and at each corner of the path meander. Each junction region has a metal patch extending therefrom. The metal patches are coupled to conducting plugs that, in turn, can be coupled to switching elements of a digital-to-analog converter unit. The junction regions can be altered to increase the precision of the voltage-dividing circuit. Because the junction regions are equidistant from the neighboring junction regions, a cell that includes the switching elements can have a square geometry.

Abstract: A driving circuit and a charging pump booster circuit capable of reducing the power consumption and the noise generated during switching. Transistors Q1 and Q2 are controlled based on a control signal input into an input terminal Tin, and a charge/discharge current is output to an output terminal Tout. The base of a transistor Q5, having almost the same characteristics as those of the transistor Q1, is connected to the base of the transistor Q1 in order to have the transistor Q5 generate a current corresponding to the turning on/off of the transistor Q1, and the current from said transistor Q5 is reflected toward a resistance element R1 by means of a current mirror circuit comprising transistors Q6 and Q7, so that base voltage of the transistor Q2 can be set lower while the transistor Q1 is on in order to hold the transistor Q2 to the OFF status. As a result, leak-through current in the transistors Q1 and Q2 can be reduced and switching noises created by said leak-through current can be reduced.

Abstract: The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region.