Abstract: A method and apparatus for uniformly solder plating leads on semiconductor packages wherein the leads are rotated during the solder plating process and the solder on the leads in planarized and solder between and bridging the leads is removed by the application of a hot gas to the device having the leads. The hot gas is preferably N2 which is inert to the process flow at the point in the process when it is utilized.

Abstract: A digital-to-analog converter having a compact “M-2M” binary-weighted ladder structure, where “M” represents an effective resistance inversely proportional to the W/L line ratio of an n-type or p-type metal oxide semiconductor (MOS) device. A reduction in the number of ladder components is accomplished by utilizing the MOS device's inherent switching function in combination with the device's resistive behavior. The ladder is comprised of a plurality of “2M” rungs, one rung for each binary bit, and each rung is comprised of a complementary pair of upper and lower MOS devices series-connected at a common node. Each device in the pair has an effective resistance of 2M ohms and only one is enabled at any given time depending upon the value of the associated binary bit. Permanently enabled MOS devices having an effective resistance of M ohms and interconnecting the common nodes of adjacent binary bit device pairs make up an “M” runner.

Abstract: A circuit for reducing speaker “pops” and “clicks” during power on and power off transitions of an op amp driver. The circuit includes an op amp 14 having a first input terminal adapted to be coupled to an input signal and a second input terminal adapted to be coupled to a reference potential. A speaker 22 is capacitively coupled to the output terminal of the op amp 14. Also included are a first current source 26 for coupling a first bias current to the op amp, and a second current source 24 for coupling a second bias current to the op amp, the first bias current being much greater than said second bias current. A switch 28, coupled between the op amp 14 and the first current source 26, is responsive to a mode control signal PWDN(bar) for enabling and inhibiting flow of the first bias current to the op amp 14. In a preferred embodiment, the op amp is an integrated circuit device, and is a metal oxide semiconductor (MOS) circuit.

Abstract: A method and apparatus for generating an output clock signal having a frequency fO derived from a reference clock signal having a frequency fR, such that f 0 = M N ⁢ f R , is satisfied, wherein M and N are integers and M<N. In the method, a plurality of intermediate clock signals are provided having a frequency fX, such that f X = 1 X ⁢ f R , wherein X is an integer close in value to N/M, and having a predetermined phase relationship with respect to one another.

Abstract: The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. A portion of the first nitride layer and of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and the first oxide layer is removed to expose a portion of the substrate under the first oxide layer. Silicon grains are formed on the pad oxide layer, the exposed portion of substrate, and the second oxide layer. The exposed portion of the substrate is then etched to leave a rugged surface on the exposed portion of the substrate.

Abstract: Multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads, and a passive surface; a leadframe for interconnecting semiconductor integrated circuits having first and second surfaces, a plurality of leads, and a chip mount pad, said leadframe being disposed between said first and second chips, and at least a portion of said passive surface of said first chip being attached to said first surface of said chip mount pad; bonding wire connections between each of said contact pads of said first chip to said first surface of one of said leads, respectively; and solder ball connections between each of said contact pads of said second chip to said second surface of one of said leads, respectively, whereby the connections to at least one of said leads are common between said first and second chips.

Abstract: A reinforced semiconductor package (20,30) and method utilizes at least one of the grooves (15,16) and ridges (24,25) formed on the package body (17,23) to reinforce the package body (17,23) to prevent warping of the package after molding.

Abstract: A post laser blown fuse slag etch for a copper fuse (30) with a barrier metal liner (18), (e.g., TaxNy, Ta, Ti, TixNy). After the fuse (30) is blown, copper and copper complexes may be selectively removed using a nitric acid and H2O2 solution. Then, a corrosion inhibitor is used to passivate the surface of exposed copper (34). Next, the barrier metal (18) of slag (22) is removed using a strong basic etch chemistry comprising a base plus H2O2. This solution removes the barrier metal selectively with respect to passivation layer (e.g., silicon nitride) (16) and oxides/FSG (12). A diluted HF solution may then be used to remove any trace metal or oxidized copper.

Abstract: The edge rate controller circuit includes: a first transistor coupled to an output control node; a second transistor coupled to the output control node; an edge rate control driver; a third transistor coupled to the first transistor; a fourth transistor coupled in parallel with the third transistor, the fourth transistor having a control node coupled to the edge rate control driver; a fifth transistor coupled to the second transistor; and a sixth transistor coupled in parallel with the fifth transistor, the sixth transistor having a control node coupled to the edge rate control driver.

Abstract: A battery protection circuit includes back-to-back connected metal-oxide-semiconductor field-effect transistors (MOSFETs). Detection circuitry detects whether the battery is in a normal charge condition, an overcharged condition, or an over-discharged condition, and for the overcharged and over-discharged conditions the circuitry asserts a corresponding enable signal. For each MOSFET, a corresponding gate voltage regulating circuit controls the gate voltage such that (i) when the corresponding enable signal is de-asserted, the gate voltage is sufficient to enable the MOSFET to strongly conduct current in either direction, and (ii) when the corresponding enable signal is asserted, the gate voltage is a function of the polarity of drain-to-source voltage of the MOSFET.

Abstract: A pressure responsive electrical switch (10) has a base (12) formed with a bottom wall (12a) having a top surface (12b) formed with a generally disc seat (12c). A recess (12d) is formed in the bottom wall through the top surface within the area defined by the disc seat and with first and second bores (12e) formed through the bottom wall aligned with the recess. Integrally formed combination terminal and movable contact arm members (14) each have a first portion (14a) serving as a respective terminal and a second, movable contact arm portion (14b) swaged to an attenuated thickness. The movable contact arm portions extend side by side transversely across the bottom surface of the recess in generally opposite directions and with a free distal contact end portion (14d) extending slightly above a disc seat formed on the top surface.

Abstract: A modified PWM space vector technique is described which includes a DC ripple voltage measurement scheme supplying feed-back to a DSP controller which then computes and generates the instantaneous PWM drives required for ripple voltage cancellation in a lightly filtered line voltage node, and executes the interface to the multi-phase power inverter circuitry. This preferably becomes a part of a closed loop motor speed control process. Use of the modified PWM drive in this manner greatly reduces the value of the filter capacitor required, allowing for the use of non-electrolytic capacitors having greater reliability and being available at lower cost.

Abstract: Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

Abstract: A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.

Abstract: A pulse rephasing circuit and method for receiving an input signal and generating an output signal includes a circuit for generating a control voltage of magnitude related to a phase difference between the input and output signals. The circuit for generating a control voltage may be, for example, a multiplier circuit to which both the input and output signals are applied. A delay circuit receives the input signal to produce an output signal that has been delayed with respect to the input signal an amount related to the magnitude of the control voltage. The delay circuit may include a capacitor, a circuit for linearly charging the capacitor, a circuit for comparing the control voltage to a voltage charged on the capacitor, and a circuit for generating a state change in the output signal when the voltage charged on the capacitor exceeds the control voltage.

Abstract: A method and apparatus for spatially and temporally multiplexing display data. The use of this method results in a bit-depth resolution higher than that achievable by the system given a number of bits of resolution. The method includes the steps of determining the desired perceived resolution (26), establishing the number of bit-planes to be used to achieve that perceived resolution (28), using at least one of those bit-planes for spatial-temporal least significant bit values (STMLSBs) (30), referencing the developed values of the STMLSBs to fractional bit gray code levels (32), developing spatial patterns (34), determining whether the spatial patterns will start in a predetermined sequence or randomly from frame-to-frame (36), loading the data onto the modulator and displaying it (38). The apparatus includes a random number generator (48) and a look up table (50) to enable the choice between random and predetermined spatial patterns, and pattern logic (46), which produces the pattern to be used.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) which uses low voltage transistors (N1, N2) to provide protection to a signal pad that handles high voltage signals during normal operation of the integrated circuit. The external signal is operable at a second supply voltage that is higher than the Vdd supply voltage. The internal circuitry of the integrated circuit is comprised of MOS transistors that have gate oxide of a first thickness that has a Vox-max suitable for the Vdd supply voltage but not for the second supply voltage. The ESD protection transistors use the same gate oxide thickness as the MOS transistors used in the internal circuitry. A substrate region in the semiconductor substrate is enclosed by a highly doped region (250) so that the back-gates of the ESD protection transistors can be voltage pumped by pump circuitry (202) in order to trigger bipolar conduction of the ESD protection transistors at a lower voltage.

Abstract: A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.

Abstract: A hot swappable system includes a first system having an electrically conductive projection and a second system. The second system includes a voltage source having a first node having a first polarity, a resistive element, and a receptor system associated with the first node and configured to receive insertion of the conductive projection. The receptor system includes first and second conductive contacts electrically connected by the resistive element. The first conductive contact is disposed relative to the second conductive contact such that insertion of the conductive projection into the receptor system causes sequential electrical contact between the conductive projection and the first contact and then between the conductive projection and the second contact.

Abstract: An efficient and practical system and method to determine when a switching DC-DC regulator is under a light load condition. The light load condition is determined by monitoring the switch node voltage to detect a zero-crossing voltage that is load dependent and occurs when the average output current minus half the switching current at the switch node is less than or equal to zero.