Abstract: A process for forming a thin film transistor having a lightly doped drain which is self-aligned with the transistor channel. A transistor gate is formed over a first dielectric layer, and a second dielectric layer is formed over the transistor gate. A layer of polycrystalline silicon (poly) is formed over said second dielectric layer, and the poly layer can be optionally doped with a P-type or N-type dopant to adjust the threshold voltage of the transistor. Next, an implant masking layer is formed over the gate, and has an etch mask thereupon. The exposed implant masking layer is removed, and in one embodiment the etch mask is undercut during the same etch to remove portions of the implant masking layer from under the etch mask. The exposed poly is doped with a P-type dopant. The etch mask is removed and the exposed poly is again doped with a P-type dopant to form the lightly doped drain using the implant mask to self-align the lightly doped drain with the channel region.

Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

Abstract: A semiconductor device comprising an element separation insulator layer (5, 6, 29) is formed to surround an active region and insulate this active region from other active regions, and to have substantially uniform height throughout its periphery on a main surface of a semiconductor substrate (1). A semiconductor layer (14) is formed flat on an entire area of the active region surrounded by this element separation insulator layer (5, 6, 29) and essentially coplanar to it. The surface of the semiconductor layer (14) is used as an element formation region. This semiconductor device can remarkably reduce an error or difference between design size of the element pattern and actual size of the element, and also can prevent a short-circuiting between conductive wirings by debris.

Abstract: A method of forming a MOS FET in which the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The sidewalls that are used to form an LDD source and drain separate a gate contact from source and drain contacts.

Abstract: A method of manufacturing an active matrix display device, in which particular emphases are laid on the forming step of an insulation layer by the ALE method and the precedent and subsequent steps thereof, thereby insulation layer being anyone among gate insulation layer, inter-busline insulation layer, protection layer and auxiliary capacitor insulation layer comprised in the display device. The method of forming the insulation layer comprises the predetermined number of repeated cycles of the steps of subjecting a substrate to the vapor of a metal inorganic/organic compound, which can react with H.sub.2 O and/or O.sub.2 and form the metal oxide, under molecular flow condition for duration of depositing almost a single atomic layer, and next subjecting the surface of thus formed metal inorganic/organic compound layer to the H.sub.2 O vapor and/or O.sub.2 gas under molecular flow condition for duration of replacing the metal inorganic/organic compound layer to the metal oxide layer.

Abstract: In a method of manufacturing an optical semiconductor element including at least the steps of forming a mask having a stripe-like gap or interval on a semiconductor substrate, epitaxially growing a semiconductor ridge including an active layer on only an exposed gap portion of the semiconductor substrate, and epitaxially growing a semiconductor cladding layer to cover the ridge, the thickness of the active layer is substantially the same as the width of the active layer.

Abstract: A method is provided for depositing aluminum thin film layers so as to form an improved metal contact in a semiconductor integrated circuit device. An initial layer of aluminum is deposited at a very low temperature, such as room temperature, to a depth sufficient to form a continuous layer. A second aluminum layer is then deposited at increasing temperatures and lower deposition rates in order to complete the deposition of the layer.

Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.

Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.

Abstract: A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).

Abstract: A process for planarizing a bonded wafer. The wafer has a layer of exposed oxide thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer for subsequent fabrication of transistors, etc.

Abstract: A method for fabricating a thin film transistor capable of increasing an ON/OFF current ratio and decreasing a consumption of electric power.

Abstract: The method of producing a CMOS transistor device. A pair of device regions are formed in separated relation from each other by a field oxide film on a pair of corresponding well regions formed in a semiconductor substrate. A gate insulating film and a gate electrode is sequentially formed on each of the device regions. The gate insulating film is removed through a mask of the patterned gate electrode to expose a silicon active surface at least in one of the device regions. A diborane gas containing P type impurity of boron is applied to the silicon active surface to form thereon a boron absorption film. N type impurity of arsenic is doped into the other device region by ion implantation to form N type of source and drain regions while masking the one device region. The boron is diffused from the adsorption film into the one device region to form P type of source and drain regions by annealing of the substrate.

Abstract: An electronic circuit apparatus which is constructed by laminating a plurality of thin films onto an insulative substrate. On the substrate, an electronic circuit element having two conductive layer which are laminated through an insulative layer is formed. The insulative layer is formed so as to cover the whole surface of the insulative substrate.

Abstract: A display panel is formed using essentially single crystal thin-film material that is transferred to substrates for display fabrication. Pixel arrays form light valves or switches that can be fabricated with control electronics in the thin-film material prior to transfer. The resulting circuit panel is than incorporated into a display panel with a light emitting or liquid crystal material to provide the desired display.

Abstract: The method comprising the steps of: depositing a semiconductor layer serving as an active layer, a first gate insulation film and an second gate insulation film on an insulation-transparent substrate, in this order; patterning the second gate insulation film using a mask for the patterning of an active region so that it is remained merely at the active region; oxidizing the semiconductor layer except for the active region using the patterned second gate insulation film as an oxidization mask, to isolate the active region from the other portion; forming a gate electrode on the second gate insulation film corresponding to the upper side of the defined active region; implanting impurity-ions in the semiconductor layer using the gate electrode as an ion-implantation mask to form a source region and a drain region; forming a protection film on the whole exposed surface of the resultant structure; forming contact holes in the protection layer so that the source region and the drain region are exposed; and forming a

Abstract: A method of manufacturing an image sensor comprising light-receiving elements, thin film transistor switching elements, and a group of lines, in which the metal electrode portion of each light-receiving element, the source and drain electrode portions of each thin film transistor switching element, and the intermediate ground wiring layer of the group of wiring lines can be formed simultaneously. As a result, the image sensor can be prepared with ease under an efficient process.

Abstract: A field-emitter having stable electrical properties, a long service life and a very small electron emission voltage is provided. The cathode of the element has a strongly sharpened projection at the tip end, and a smooth connection between the projection and the body portion. In the method of manufacturing the elements, cathodes are produced with a high reproducibility by using a mold produced by forming concave portions in the silicon and oxidizing the layer thereon, whereby the spacing between the cathode and the gate electrode is determined by the thickness of the silicon oxide layer, and the position of the cathode is determined by the silicon oxide layer embedded in the silicon substrate, by using an etching stop method based on an electrochemical etching process.

Abstract: A resistor (45) of semiconductor material is formed on an insulating layer (42), then a silicon nitride film (46) is deposited on the entire surface including the resistor (45), and a silicon dioxide film (47) is sequentially deposited thereon, and thereafter electrodes (49A) and (49B)of the resistor (45) are formed, thereby preventing the fragility of the insulating layer (51) at step portions of the resistor (45), preventing the breakage of the electrodes and interconnections, and improving a withstand voltage between the resistor (45) and the interconnections crossing over it to thereby improve yield of a semiconductor device.

Abstract: A semiconductor layer undergoes isolation etching and gate recess etching, using a side wall insulating layer having the shape of a forward taper as a mask, by means of the anisotropic etching technique. The shape of the side wall of the semiconductor layer corresponds to that of the forward taper of the mask. The shape of the forward taper is always constant, irrespective of face orientation of crystal of the semiconductor layer. Since the taper angle of the side wall insulating layer can freely be set within a predetermined range in accordance with conditions, the taper angle of the semiconductor layer can be controlled. The design margin of an electrode wiring pattern is greatly improved. Since the side wall of a gate recess is stably formed in the shape of a forward taper, the side wall insulating layer can be formed on the surface of the forward taper and thus a gate electrode layer can be formed so as to have a T-shaped cross section. Therefore, the gate resistance can be greatly reduced.