Patents Examined by Michael Trinh
  • Method of manufacturing an insulated gate FET having double-layered wells of low and high impurity concentrations
    Patent number: 5420062
    Abstract: This invention relates to an insulated gate FET in which the withstanding voltage and the latch-up resistant property are both made high. The structure thereof includes a second well formed in a first well and having an impurity concentration lower than that of the first well. Source and drain electrodes of the FET are formed in the second well.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: May 30, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nakfumi Inada, Osamu Takata
  • Method for forming a wiring layer
    Patent number: 5420077
    Abstract: A method for a wiring layer on a semiconductor substrate wherein a contact hole for a wiring layer is formed by laminating a lower insulating layer and an etching barrier layer on the semiconductor substrate providing electrodes via a gate insulating film, forming a hole in the etching barrier layer using a first mask pattern having a hole pattern in which a diameter of the hole thereof is larger than that of the contact hole to be formed, laminating an upper insulating layer and a second mask pattern having a hole pattern in which a diameter of the hole thereof is substantially the same as that of the contact hole, subjecting the lower and upper insulating layers and the gate insulating film to an isotropic etching and an anisotropic etching, utilizing the second mask pattern, thereby forming a contact hole having no exposure of the etching barrier layer at the side of wall of the contact hole.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: May 30, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Saito, Keizo Sakiyama
  • Method of reducing leakage current in an integrated circuit
    Patent number: 5416030
    Abstract: A method is provided for reducing leakage current in an integrated circuit (24). A first doped region (18) having a first conductivity type is formed in a semiconductor layer (10) having a second conductivity type, such that a second doped region (20) having the first conductivity type is formed in the semiconductor layer (10). The second doped region (20) is less conductive than the first doped region (18). The first doped region (18) is removed from the semiconductor layer (10), such that the second doped region (20) substantially remains in the semiconductor layer (10). The integrated circuit (24) is formed to include the second doped region (20) and the semiconductor layer (10).
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: May 16, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Lissa K. Magel
  • Integrated circuit and manufacture
    Patent number: 5416033
    Abstract: A method of semiconductor integrated circuit fabrication including a technique for forming punch-through control implants is disclosed. After gate formation, a dielectric is formed which covers the gate and exposed portions of a semiconductor substrate. The dielectric is formed by a process which makes that portion of the dielectric adjacent the gate sidewalls more vulnerable to wet etching than those portions of the dielectric which are adjacent the top of the gate and the exposed substrate. The dielectric is then subsequently etched to form channels adjacent the gate which exposed the substrate and served to collimate an ion implantation beam. The remaining portions of the dielectric may then be stripped away and conventional procedures employed to form source and drain. Illustratively, the dielectric is formed from TEOS to which NF.sub.3 is added during the deposition process. The addition of NF.sub.
    Type: Grant
    Filed: February 7, 1994
    Date of Patent: May 16, 1995
    Assignee: AT&T Corp.
    Inventors: Kuo-Hua Lee, Chung-Ting Liu, Kurt G. Steiner, Chen-Hua D. Yu
  • Method for manufacturing a liquid crystal display substrate
    Patent number: 5413958
    Abstract: An amorphous silicon film is formed on a glass substrate by a CVD method, and then the island regions of the amorphous silicon film is changed to a plurality of polycrystalline silicon regions which are arranged in a line and apart with each other in a predetermined distanced by intermittently irradiating laser pulses each having the same dimensions as those of the island region onto the amorphous silicon film, using a laser beam irradiating section. Switching elements including the island regions as semiconductor regions are formed by etching and film-forming process to constitute a driving circuit section. The section is divided to gate driving circuit sections and source driving circuit sections for driving thin film transistors formed in a pixel region.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: May 9, 1995
    Assignee: Tokyo Electron Limited
    Inventors: Issei Imahashi, Kiichi Hama, Jiro Hata
  • Method of manufacturing thin film transistors in a liquid crystal display apparatus
    Patent number: 5407845
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: April 18, 1995
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • MOS manufacturing process having reduced gate insulator defects
    Patent number: 5407839
    Abstract: A method for reducing implant-induced damage and residual photo-resist-induced damage to a gate insulator layer first forms a gate insulator layer on portions of a semiconductor substrate. A first gate electrode layer is formed over the gate insulator layer, this first gate electrode layer being thinner than the desired final gate electrode thickness. A threshold adjustment implant is performed through the first, thin, gate electrode layer and underlying gate insulator layer. A second gate electrode layer is formed over the first gate electrode layer such that the thickness of the first and second gate electrode layers are substantially equal to the desired final gate electrode thickness. The first and second gate electrode layers are then patterned concurrently by conventional photolithography processes to form the gate electrodes.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: April 18, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Yutaka Maruo
  • Method for forming a linear field effect transistor
    Patent number: 5405793
    Abstract: In one form of the invention, a field effect transistor is disclosed, the transistor comprising: a channel between a source and a drain, the channel comprising: a first region 22 of a first semiconductor material having a first doping concentration; a second region 20 of a second semiconductor material having a second doping concentration, the second region 20 lying above the first region 22; a third region 18 of the first semiconductor material having a third doping concentration, the third region lying above the second region 20, wherein the first doping concentration is higher than the second and third doping concentrations; and a gate electrode 12 lying above the third region 18, whereby an electrical current flows in the channel primarily in the first region 22 or primarily in the second region 20 by varying a voltage on the gate electrode 12.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: April 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Pertti K. Ikalainen, Larry C. Witkowski
  • Method of making a HgCdTe thin film transistor
    Patent number: 5403760
    Abstract: Group II-VI thin film transistors, a method of making same and a monolithic device containing a detector array as well as transistors coupled thereto wherein, according to a first embodiment, there is provided a group II-VI insulating substrate, a doped layer of a group II-VI semiconductor material disposed over the substrate, an insulating gate region disposed over the doped layer, a pair of spaced contacts on the doped layer providing source and drain contacts, a gate contact disposed over the insulating gate region, an insulating layer disposed over exposed regions of the substrate, doped layer, insulating gate region and contacts and metallization disposed on the insulating layer and extending through the insulating layer to the contacts. The thickness of the doped layer is less than the maximum depletion region thickness thereof.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: April 4, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Richard A. Schiebel, Michael A. Kinch, Roland J. Koestner
  • Method of fabricating a thin film transistor
    Patent number: 5403761
    Abstract: This invention relates to the Thin Film Transistor having the self-aligned diffused source/drain regions for improving the ratio of on to off current and the method of fabricating the same.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: April 4, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Sa K. Rha
  • Method for hydrogenating thin film transistor by using a spin-on-glass film
    Patent number: 5401685
    Abstract: A method for hydrogenating a thin film transistor, capable of making a sufficient amount of hydrogen penetrate a channel polysilicon of the thin film transistor, thereby reducing the amount of leakage current at a turn-off state of the thin film transistor while increasing the amount of drive current at a turn-on state of the thin film transistor so as to improve the characteristic of the thin film transistor. The method includes the steps of depositing an insulating film as a metal electrode protective film over a thin film transistor, which has been subjected to a patterning for forming metal electrodes, coating a silicon-on-glass film over the insulating film, and depositing another insulating film over the silicon-on-glass film so as to prevent hydrogen contained in the silicon-on-glass film from being externally leaked when the silicon-on-glass film is subsequently subjected to heat treatment.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: March 28, 1995
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Hyoung C. Ha
  • Method of fabricating a field-effect transistor over gate electrode
    Patent number: 5401665
    Abstract: A field-effect transistor in which a metal gate (14) is defined on top of an insulating substrate (12). A free-standing semiconductor thin film (16), obtained by the epitaxial lift-off process, is bonded to both the top of the metal gate and the insulating substrate. Electrodes (20, 22) attached to the top of ends of the semiconductor film complete the transistor.
    Type: Grant
    Filed: January 5, 1994
    Date of Patent: March 28, 1995
    Assignee: Bell Communications Research, Inc.
    Inventor: Winston K. Chan
  • Method of manufacturing thin film transistor
    Patent number: 5397718
    Abstract: In a method of manufacturing a thin film transistor, when impurity ions are introduced in a channel region between source and drain regions in a semiconductor layer, an insulator layer is first formed on the semiconductor layer. Then, impurity ions generated on high frequency discharge are introduced through the insulator layer into the semiconductor layer under a specified acceleration voltage. Then, the introduction depth of impurities and the amount of the impurities to be introduced in the channel region can be controlled or the threshold voltage of the thin film transistor can be controlled. This method can be applied to a large substrate.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: March 14, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mamoru Furuta, Tetsuya Kawamura, Tatsuo Yoshioka, Hiroshi Sano, Yutaka Miyata
  • Method for manufacturing a display panel
    Patent number: 5397719
    Abstract: The present invention relates to an improved method of manufacturing pads of a display panel. Al or Al alloy is deposited and patterned on a glass substrate for forming a plurality of gate electrodes and lines. Then a plurality of pads are formed with Ta or Ti, which is capable of forming an anodic oxide thereof; each pad extending over an edge of each of the respective gate lines to provide an electrical coupling therebetween. Thereafter, the entire surface of the pads, gate electrodes and lines is subjected to an anodic oxidation under a high anodization voltage. Anodic oxide layers on the pads are then etched away together with a silicon nitride layer during a subsequent pad opening processing step. Consequently, in accordance with the invention, a photoresist masking process for the selective anodic oxidation of Al gate lines and electrodes is eliminated.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: March 14, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Soo Kim, In-Sik Jang, Dong-Kyu Kim, Yong-Kuk Bae
  • Method of making a semiconductor device
    Patent number: 5397743
    Abstract: A method of making a semiconductor device capable of simplifying the overall manufacturing processes and carrying out the reliable interconnections between wires.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: March 14, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventors: Young K. Jun, Chang J. Lee
  • Integrated partial sawing process
    Patent number: 5393706
    Abstract: A process for partially sawing the streets on semiconductor wafers. After sawing the streets can be covered by a protective material, and then the wafer continues its processing as before. After the wafer is broken, the protective material may or may not be removed. Additionally, the wafer may be broken into individual chips using a wedge piece that has a number of individual wedges on it, where the individual wedges press against the partially sawn streets, causing the wafer to break.
    Type: Grant
    Filed: January 7, 1993
    Date of Patent: February 28, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Michael A. Mignardi, Rafael C. Alfaro
  • Process for fabricating submicron single crystal electromechanical structures
    Patent number: 5393375
    Abstract: A process for fabricating submicron movable mechanical structures utilizes chemically assisted ion beam etching and reactive ion etching which are independent of crystal orientation. The process provides released mechanical structures which may be of the same material or of different materials than the surrounding substrate, and a nitride coating may be provided on the released structure for optical applications.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: February 28, 1995
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Noel C. MacDonald, Zhoying L. Zhang, Gyorgy A. Porkolab
  • Method of producing a multi-stage amplifier device
    Patent number: 5391512
    Abstract: A multistage amplifier device including an amplifier at the first stage or each of active elements of amplifiers at plural stages containing the first stage and excluding the last stage which is formed of FETs 1a and 1b including a gate having a self-alignment structure, and amplifiers at the remaining subsequent stages which are formed of FETs 1c and 1d including a gate electrode on an operating layer sandwiched between source and drain high impurity density regions, one edge portion at a source side of the gate electrode being overlapped through an insulating layer with the source high impurity density region while the other edge portion at a drain side of the gate electrode does not expand to the drain high impurity density region.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: February 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Nobuo Shiga
  • Method of manufacturing a semiconductor device comprising an insulated gate field effect device
    Patent number: 5387528
    Abstract: A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7).
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: February 7, 1995
    Assignee: U.S. Philips Corporation
    Inventors: Keith M. Hutchings, Andrew L. Goodyear, Andrew M. Warwick
  • Method of forming an etched ohmic contact
    Patent number: 5387548
    Abstract: The present invention includes forming an etched ohmic contact (10, 9) by applying a layer of an etch susceptible contact material (14) to a III-V semiconductor substrate (11). A portion of the contact layer (14A) is alloyed with the substrate (11) to form are etch resistant area (14A) of the contact layer. The contact layer (14) is selectively etched to remove etch susceptible portions of the contact layer while leaving the etch resistant area (14A) on the substrate (11). Another alloy operation is performed to form ohmic contact between the etch resistant area (14A) and the substrate (11). Consequently, an etch ohmic contact (10, 9) that is substantially devoid of gold is formed.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: February 7, 1995
    Assignee: Motorola, Inc.
    Inventor: Jaeshin Cho