Patents Examined by Minh Trinh
  • Patent number: 7197817
    Abstract: Disclosed is a method of forming bump electrodes on wired circuit boards. A high-concentration impurity Si template doped with boron and having a pit formed therein is prepared. A plated resist is formed on the high-concentration impurity Si template and an opening is formed at the position of the pit. Then, an electric field is applied to the high-concentration impurity Si template and Au is buried in the opening in the plated resist to form a Au-plated buried layer. An electrode pad is formed on a semiconductor chip. With the plated resist separated from the high-concentration impurity Si template, the electrode pad of the semiconductor chip is aligned with the Au-plated buried layer and is bonded by thermo-compression bonding. The Au-plated buried layer is transferred to the electrode pad to form an Au bump on the semiconductor chip.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: April 3, 2007
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Nobuaki Takahashi, Yuji Akimoto, Mikio Oda, Hikaru Kouta
  • Patent number: 7191517
    Abstract: A radiation shielding structure includes a first adhesive layer, a resin layer, and a metal foil laminated sequentially on a release layer of a plastic film. A metal layer pattern is formed from the metal foil. The first adhesive layer, the resin layer, and the metal layer pattern are formed sequentially from the bottom on a transparent substrate by separating the release layer from the first adhesive layer along an interface and then adhering the first adhesive layer to the transparent substrate.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 20, 2007
    Assignee: Kyodo Printing Co., Ltd.
    Inventors: Masayoshi Shimamura, Ryohei Okamoto, Yoshiyuki Atsuchi
  • Patent number: 7191515
    Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Robert C. Sundahl, Kenneth Wong
  • Patent number: 7191512
    Abstract: The present invention provides a tray for holding components having first and second sides, wherein the first side has at least one first component receptacle for engaging said component; and the second side has at least one component engaging member, and further wherein the first component receptacle and the component engaging member are aligned such that when multiples of the tray are stacked upon each other the first component receptacle and the component engaging member will cooperate to restrain the motion of the component relative to the tray. In such an embodiment the component will have first and second engagement surfaces and the first component receptacle will engage the first component engagement surface and the component engaging member will engage the second component engagement surface.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: March 20, 2007
    Assignee: Applied Kinetics, Inc.
    Inventors: Mark T. Girard, Ryan A. Jurgenson, Susan June Livermore, legal representative, David R. Swift, Joseph P. Tracy, Roger R. Livermore, deceased
  • Patent number: 7191518
    Abstract: A hyperboloid contact socket is provided which comprises a tubular body of conductive material and preferably having at one end a lip defining an entrance aperture for receiving a mating pin terminal and having on the opposite end a termination of an intended configuration for attachment to a circuit board or other device or item. The tubular body contains a plurality of conductive wires conductively and permanently affixed at their respective ends torespective inner surfaces at or near the outer and inner ends of the body and disposed in an angular disposition to the longitudinal axis to form the shape of a single sheet hyperboloid. In one aspect of the invention a mandrel employed to orient the wires within the tubular body during fabrication of the contact socket remains attached to the tubular body after assembly of the contact wires and serves as a connecting pin to which various terminations can be attached.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: March 20, 2007
    Assignee: QA Technology Company, Inc.
    Inventors: Victor Beloritsky, Thomas D. Coe, Robert P. Lascelles, W. William Podszus
  • Patent number: 7191516
    Abstract: A high reliability radiation shielding integrated circuit device comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose tolerance of the circuit die. An integrated circuit device for use in high reliability applications. The integrated circuit device is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: March 20, 2007
    Assignee: Maxwell Technologies, Inc.
    Inventor: Janet Patterson
  • Patent number: 7188415
    Abstract: A cable assembly comprises a plurality of electrical or fiber-optic cables, a spacer, and a collar. The cables are arranged lengthwise in a bundle, which includes a segment having a cross-sectional arrangement organized into a plurality of columnar sections of contiguous cables. Each columnar section has at least one cable. The spacer is disposed between adjacent columnar sections of cables and thus forms a dividing line between the adjacent columnar sections. The spacer spans substantially entirely across a cross section of the segment of the bundle in one direction. The collar is disposed entirely around the bundle and the spacer along at least a portion of the segment. The collar is sufficiently tight such that the collar and the spacer cooperate to hold the adjacent columnar sections in substantially fixed relative positions within the cross-section of the bundle.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: March 13, 2007
    Assignee: Carlyle, Inc.
    Inventors: Paul W. Robinson, Terry M. Kleeberger, Billie D. Eliot
  • Patent number: 7188409
    Abstract: The present invention features a method wherein a component in a multi-head component placement machine is rejected during the placement cycle. A component is imaged and the image processed using an automated vision system. The image processing determines whether the component is placeable based upon a comparison of the component image to preprogrammed mechanical parameters for the component. A non-placeable component is rejected into a reject station, which is contiguous with the head. Because a component can be rejected during the placement cycle, there is no slowdown of the placement machine cycle rate.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: March 13, 2007
    Assignee: Universal Instruments Corp.
    Inventor: Koenraad Gieskes
  • Patent number: 7188408
    Abstract: A method of making an electrical connector includes the steps of: providing a connector body (2) having an insert (5) defining a recessed area (54a) at one side and a number of channels (54b) at an opposite side; assembling a ground bus (4) to the recessed area of the insert, the ground bus including a carrier strip (46) with a number of fingers (460) extending therefrom; assembling a number of signal contacts (3) to the channels of the insert, each signal contact including a board mounting portion (32); and displacing the carrier strip such that each finger extends into space (320) between the mounting portions of two adjacent signal contacts.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 13, 2007
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Iosif R. Korsunsky, Joanne E. Shipe, Robert W. Brown
  • Patent number: 7188410
    Abstract: A printed circuit board and method for reducing the impedance within the reference path and/or saving space within the printed circuit board. In one embodiment of the present invention, a printed circuit board comprises a plurality of conductive layers. The printed circuit board further comprises two or more vias for interconnecting two or more conductive layers. The printed circuit board further comprises an electrical component embedded in a particular via between two conductive layers to reduce the impedance within the reference path and/or save space within the printed circuit board.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Timothy Wayne Crockett, Harry Thomas Minikel
  • Patent number: 7188413
    Abstract: A microelectronic element is formed from a structure including metal layers on top and bottom sides of a dielectric. Apertures are formed in the top metal layer, and vias are formed in the dielectric in alignment with the apertures. Top and bottom conductive features are formed in proximity to the vias, as by selectively depositing a metal on the metal layers or selectively etching the metal layers. The top and bottom conductive features are connected to one another by depositing a conductive material into the vias, most preferably without seeding the vias as, for example, by depositing solder in the vias.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 13, 2007
    Assignee: Tessera, Inc.
    Inventor: Owais Jamil
  • Patent number: 7188406
    Abstract: Disclosed are methods of manufacturing electrical cables. In one embodiment of the invention, method for manufacturing a wellbore cable includes providing at least one insulated conductor, extruding a first polymeric material layer over the insulated conductor, serving a first layer of armor wires around the polymeric material and embedding the armor wires in the first polymeric material by exposure to an electromagnetic radiation source, followed by and extruding a second polymeric material layer over the first layer of armor wires embedded in the first polymeric material layer. Then, a second layer of armor wires may be served around the second polymeric material layer, and embedded therein by exposure to an electromagnetic radiation source. Finally, a third polymeric layer may be extruded around the second layer of armor wires to form a polymeric jacket.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: March 13, 2007
    Assignee: Schlumberger Technology Corp.
    Inventors: Joseph P. Varkey, Byong Jun Kim
  • Patent number: 7185430
    Abstract: A method of manufacturing contact sheets is provided, including the steps of providing an electrically conductive sheet to form a conductive member. The conductive member includes a plurality of adjacent contact members joined by a plurality of linking portions. At least one base sheet is provided having a plurality of openings formed therein. The conductive member is positioned and secured to at least one surface of the base sheet such the contact members are positioned in the openings. The contact members are processed to (i) sever the linking portions from adjacent contact members and (ii) to form extending contact portions having a predetermined configuration. The position of the linking portions prior to severing is such that opposing severed faces of the linking portions are separated from each other and the contact members are electrically insulated from one another.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: March 6, 2007
    Assignee: NGK Insulators, Ltd.
    Inventor: Toshimasa Ochiai
  • Patent number: 7185429
    Abstract: A flexible multilayer wiring board manufactured by laminating a metal foil via an insulating layer to cover the first layer circuit wiring formed on a conductive substrate, and a resist layer is formed to cover the second layer circuit wiring formed by pattern-etching the metal foil. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, into interlayer via holes each formed applying a laser beam to the resist layer to establish interlayer connection between the first and second layer circuit wirings. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, into hole portions of an insulating layer formed to cover the second layer circuit wiring to form external connection terminals. Then, the conductive substrate is removed entirely or partly to expose the first layer circuit wiring.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: March 6, 2007
    Assignees: Sony Corporation, Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Hidetoshi Kusano, Shinji Kumon
  • Patent number: 7185420
    Abstract: An apparatus is provided for thermally coupling a heat dissipation device to a microelectronic device. A thermal compression bonding apparatus is provided comprising a bonding head adapted to apply heat and pressure to the heat dissipation device to provide the desired thermal profile to effect solidification of the interface material from the center outward.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventor: Steve M. Mayer
  • Patent number: 7181840
    Abstract: An improved manufacturing method for a gas sensor is provided which is capable of establishing a required hermetic seal in a body of the gas sensor. The method includes preparing a sensor assembly including a housing, an air cover, an insulation porcelain, and a sensor element, pressing the air cover against the housing to fit an end of the air cover on an end of the housing to form an overlap thereof, and welding the air cover to the housing over the overlap. The welding is accomplished while pressing the air cover against the housing, thereby compressing an elastic member in the air cover to establish a hermetic seal between the sensor element and the housing.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: February 27, 2007
    Assignee: Denso Corporation
    Inventors: Hirokazu Yamada, Masato Ozawa
  • Patent number: 7181834
    Abstract: Method for fabricating a textured dielectric substrate (400) for an RF circuit. The method can include the step (104) of selecting a plurality of dielectric substrate materials, each having a distinct combination or set of electrical properties that is different from the combination of electrical properties of every other one of dielectric substrate materials. Selecting a textured substrate pattern (106) which is comprised of at least two types of distinct areas respectively having the distinct sets of electrical properties, with each distinct area dimensioned much smaller than a wavelength at a frequency of interest. Cutting the dielectric substrate materials (202, 204) into a size and shape consistent with the distinct areas of the selected pattern so as to form a plurality of dielectric pieces (206, 208). Arranging the dielectric pieces on a base plate (302) in accordance with the selected pattern to form the textured dielectric substrate.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 27, 2007
    Assignee: Harris Corporation
    Inventors: Dennis Tebbe, Thomas Smyth, Terry Provo, Dara Ruggiero
  • Patent number: 7178220
    Abstract: Methods for manufacturing slot core inductors and transformers includes using large scale flex circuitry manufacturing methods and machinery for providing two mating halves of a transformer winding. One winding is inserted into the slot of a slot core and one winding is located proximate to the exterior wall of the slot core. These respective halves are joined together using solder pads or the like to form continuous windings through the slot and around the slotted core.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: February 20, 2007
    Assignee: Multi-Fineline Electronix, Inc.
    Inventor: Philip A. Harding
  • Patent number: 7178236
    Abstract: A method for constructing a membrane probe that includes providing a substrate, and creating a depression within the substrate. Conductive material is located within the depression and a conductive trace is connected to the conductive material. A membrane is applied to support the conductive material and the substrate is removed from the conductive material.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: February 20, 2007
    Assignee: Cascade Microtech, Inc.
    Inventors: Reed Gleason, Michael A. Bayne, Kenneth Smith
  • Patent number: 7178229
    Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: February 20, 2007
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Matthew C. Snogren, Richard H. Snogren