Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, a seed metal layer may be used to grow hard metal layers above it for handling. Metal may be plated above these metal layers everywhere except where a block of stop electroplating (EP) material exists. The stop EP material may be obliterated, and a barrier layer may be formed above the entire remaining structure. The substrate may be removed, and the individual dies may have any desired bonding pads and/or patterned circuitry added to the semiconductor surface. The remerged hard metal after laser cutting and heating should be strong enough for handling. Tape may be added to the wafer, and a breaker may be used to break the dies apart. The resulting structure may be flipped over, and the tape may be expanded to separate the individual dies.

Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

Abstract: A coated aluminum component for a substrate processing chamber comprises an aluminum component having a surface; a first aluminum oxide layer formed on the surface of the aluminum component, the aluminum oxide layer having a surface comprising penetrating surface features; and a second aluminum oxide layer on the first aluminum oxide layer, the second aluminum oxide layer substantially completely filling the penetrating surface features of the first aluminum oxide layer. A method of forming the coated aluminum component is also described.

Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: A gate assembly comprising a gate mount and a gate mounted for movement on the gate mount between an opened position and a closed position. The gate assembly further comprises an illumination system mounted on the gate mount for turning on a light mounted on the gate mount when someone approaches the gate when it is dark in the vicinity of the gate.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: An apparatus for interfacing a test head to a peripheral system is provided. The apparatus includes a first unit having a first connection member for providing electrical communication with the peripheral system, a second unit having a second connection member for providing electrical communication with the test system, and pivot members coupling the first unit and the second unit. The pivot members enable motion in the following sequence as one of the first and second unit moves towards the other: a) pivotal motion between the first connection member and the second connection member; and b) linear motion which decreases linear distance between the first connection member and the second connection member while maintaining respective contact surfaces of the first and second connection members in parallel.

Abstract: A two or three component lens system. The first component is a ring-like supporting component that is implanted in the capsular bag following cataract surgery. The first component is a non-optical component and does not correct for any refractive errors. The first component may contains features to help reduce or eliminate PCO. The second component is an optical component that may contain all of the corrective optical power of the lens system. The second component has a pair of tabs for locking the second component within the first component. The third component is optional and is similar to second component and contains some optical power to correct for any residual optical error not corrected by the second component. The second and third components may also be implanted so as to move relative to one another, thereby providing some accommodation.

Abstract: The invention is directed to a data storage device that includes a host connector to facilitate attachment to a host computer so that the host computer can access one or more storage elements within the device. The data storage device includes a flexible member to mechanically and electrically couple the host connector of the device to a housing that holds the storage elements. The housing may comprise a receptacle for insertion of the host connector when the device is not coupled to a host computer. The flexible member may define a length and a flexibility sufficient to allow the host connector to be inserted into the receptacle in the housing. When the host connector is inserted into the receptacle in the housing, the data storage device forms a loop, allowing the device to be attached to items or objects or possibly worn as jewelry.

Abstract: According to one aspect of the present invention, a gaming machine for conducting a wagering game includes a display for displaying a plurality of symbols on a plurality of reels defining an array. The array includes a plurality of player-selectable paylines indicating symbol combinations in the array. The gaming machine also includes a player-input device, a payline indicator, and a controller. The player-input device receives input from a player for selecting one or more of the player-selectable paylines. The payline indicator is movable along a vertical path in a direction alongside the plurality of reels and indicates a number corresponding to the selected ones of the player-selectable paylines. The controller is in communication with the display and is programmed to activate the selected ones of the player-selectable paylines during the wagering game.

Abstract: A hermetic pressure connector which provides a pressure-tight, electrically conductive connection through a hole in a bulkhead. The connector includes a transverse support member having a high pressure side and an opposite low pressure side. A passage extends through the transverse support member between the opposite sides. A conductor pin having an axial portion extends through the passage. An insulating sleeve surrounds at least the axial portion of the conductor pin, thereby electrically insulating the transverse support member from the conductor pin. A molded connected body surrounds at least a central portion of the conductor pin at least at one of the high and low pressure sides to thereby mechanically support the conductor pin in the passage. The molded connector body is directly sealingly engaged with the conductor pin, the insulating sleeve and the transverse support member.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.