Patents by Inventor Wen Hsu

Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10416409
    Abstract: An optical system includes a base, a first lens driving module, and a second lens driving module. The first lens driving module includes a first lens holder, a first magnet, and a first coil. The first lens holder is configured to hold a first optical element. The first coil corresponding to the first magnet is configured to drive the first lens holder to move relative to the base. The second lens driving module includes a second lens holder, a second magnet, and a second coil. The second lens holder is configured to hold a second optical element. The second coil corresponding to the second magnet is configured to drive the second lens holder to move relative to the base. The first magnet is disposed between the first and second lens holders, and no other magnet is disposed between the first and second lens holders except the first magnet.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 17, 2019
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kuo-Chun Kao, Nai-Wen Hsu, Shih-Ting Huang, Shao-Chung Chang, Sin-Jhong Song
  • Publication number: 20190279876
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10403189
    Abstract: In some examples, a computing device includes a first display in a first housing and a second display in a second housing. The computing device may determine an angle between the first display device and the second display device, determine a first temperature map of the first housing based on the angle and first temperature data received from a first set of temperature sensors in the first housing, and determine a second temperature map of the second housing based on the angle and second temperature data received from a second set of temperature sensors in the second housing. The computing device may determine a temperature difference between the first display device and the second display device, determine a remedial action, and perform the remedial action to reduce the temperature, color, and/or color intensity difference between the first display device and the second display device.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 3, 2019
    Assignee: Dell Products L.P.
    Inventors: Deeder M. Aurongzeb, Joohyun Woo, Claire Hao Wen Hsu
  • Patent number: 10393718
    Abstract: A MEMS apparatus for thermal energy control including a sensor and an IC chip is provided. The sensor includes a heating device for heating a sensing element and a detecting device for detecting a physical quantity. The IC chip includes a memory unit for storing a target value of the sensing element and a data processing unit for convert the physical quantity to a converted value, where a gap value is defined by subtracting the converted value from the target value. Besides, a control unit of the IC chip sets a parameter value according to the gap value, and a driving unit adjusts a quantity of thermal energy generated by the heating device according to the parameter value to reduce heating time and frequency of the heating device thereby reducing electrical power consumption. The MEMS apparatus is applicable to MEMS sensors requiring controlled operating temperature, such as a gas sensor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 27, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Wen Hsu, Ying-Che Lo, Chao-Ta Huang, Li-Tao Teng
  • Patent number: 10395974
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate at low cost and with low total thickness variation (TTV). In some embodiments, an etch stop layer is epitaxially formed on a sacrificial substrate. A device layer is epitaxially formed on the etch stop layer and has a different crystalline lattice than the etch stop layer. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates. The sacrificial substrate is removed. An etch is performed into the etch stop layer to remove the etch stop layer. The etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Pei Chou, Hung-Wen Hsu, Jiech-Fun Lu, Yu-Hung Cheng, Yung-Lung Lin, Min-Ying Tsai
  • Patent number: 10388763
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, Chiung Wen Hsu, Yu-Ting Weng
  • Patent number: 10386597
    Abstract: A moving mechanism for holding a lens is provided, including a carrier having an accommodating space, a coil, a sensing object, a base, at least one magnetic member, and a position detector, wherein the lens is disposed in the accommodating space. The coil and the sensing object are disposed on the carrier, and the coil surrounds the accommodating space. At least a portion of the coil is disposed between the sensing object and the accommodating space. The magnetic member and the position detector are disposed on the base, and the position detector is adjacent to the sensing object. When a current flows through the coil, the carrier moves relative to the base.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: August 20, 2019
    Assignee: TDK TAIWAN CORP.
    Inventor: Nai-Wen Hsu
  • Publication number: 20190250513
    Abstract: Various embodiments of the present application are directed towards an edge-exposure tool with a light emitting diode (LED), as well as a method for edge exposure using a LED. In some embodiments, the edge-exposure tool comprises a process chamber, a workpiece table, a LED, and a controller. The workpiece table is in the process chamber and is configured to support a workpiece covered by a photosensitive layer. The LED is in the process chamber and is configured to emit radiation towards the workpiece. A controller is configured to control the LED to expose an edge portion of the photosensitive layer, but not a center portion of the photosensitive layer, to the radiation emitted by the LED. The edge portion of the photosensitive layer extends along an edge of the workpiece in a closed path to enclose the center portion of the photosensitive layer.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Ying-Hao Wang, Chia-Chi Chung, Han-Chih Chung, Yu-Xiang Lin, Yu-Shine Lin, Yu-Hen Wu, Han Wen Hsu
  • Publication number: 20190252325
    Abstract: A chip package structure including a first circuit structure, a chip, an electronic device, a first encapsulant, a second encapsulant, a plurality of through pillars, and an electromagnetic interference (EMI) shielding layer is provided. The chip has an active surface facing the first circuit structure. The electronic device has a connection surface facing the first circuit structure. The chip and the electronic device are disposed on opposite sides of the first circuit structure respectively. The first encapsulant encapsulates the chip. The second encapsulant encapsulates the electronic device. The through pillars penetrate the first encapsulant and are electrically connected to the first circuit structure. The EMI shielding layer covers the first encapsulant and the second encapsulant. The chip or the electronic device is grounded by the EMI shielding layer.
    Type: Application
    Filed: July 16, 2018
    Publication date: August 15, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Yu-Wei Chen, Hsuan-Chih Chang, Yuan-Fu Lan, Hsien-Wen Hsu
  • Publication number: 20190252423
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 15, 2019
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 10381268
    Abstract: A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 13, 2019
    Assignees: NIKO SEMICONDUCTOR CO., LTD., SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu
  • Publication number: 20190244934
    Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Patent number: 10373992
    Abstract: Compact camera modules that may be used in small form factor devices. The camera module may include a lens holder configured to receive one or more lens elements and a photosensor. In some embodiments, the lens holder may define a first recess for receiving the lens elements and a second recess for receiving one or more other components, such as the photosensor. In some embodiments, the photosensor may be configured to communicate with a flex circuit board without coupling the photosensor to a substrate to form a flip chip that communicates with the flex circuit board. The photosensor may be optically aligned with the lens elements and bonded to the lens holder such that the photosensor is fixed in an aligned position and at least partially enclosed by the lens holder.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 6, 2019
    Assignee: Apple Inc.
    Inventors: Ya Wen Hsu, Douglas S. Brodie, Steven Webster
  • Publication number: 20190227203
    Abstract: An optical lens assembly includes at least two lens elements and at least one light blocking sheet. Each of the lens elements includes a connecting structure for aligning the two lens elements. Each of the connecting structures includes a connecting surface and a circular conical surface, and a receiving space is formed between the two lens elements. A vertical distance between the receiving space and an optical axis is shorter than a vertical distance between each circular conical surface and the optical axis. The light blocking sheet is received in the receiving space and has a polygonal opening, and an outside diameter of the light blocking sheet is smaller than or equal to a minimum diameter of each circular conical surface.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Chih-Wen HSU, Ming-Ta CHOU
  • Patent number: 10361234
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10359599
    Abstract: A lens driving module is provided which includes a movable portion, a base, a housing, a plastic substrate, and a 3D circuit. The base is adjacent to the movable portion, and the housing is connected to the base and surrounds the movable portion. The plastic substrate is disposed between the housing and the movable portion. At least a portion of the 3D circuit is disposed on the plastic substrate and is configured to transmit the signals or power for the operation of the lens driving module. The 3D circuit has an inner connecting portion and an outer connecting portion positioned on different planes and arranged to be parallel to each other.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 23, 2019
    Assignee: TDK TAIWAN CORP.
    Inventors: Shang-Yu Hsu, Nai-Wen Hsu
  • Patent number: 10354978
    Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 16, 2019
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Publication number: 20190214366
    Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Publication number: 20190214367
    Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu, Li-Chih Fang
  • Publication number: 20190201736
    Abstract: A crank apparatus includes a crank arm having at least one cavity on one of the surfaces of the crank arm, at least one thin material layer embedded within the at least one cavity and having an exposed outer surface, and at least one sensing element attached to the outer surface of the thin material layer. The crank arm is manufactured of a material with non-uniform strain characteristics, the thin material layer is manufactured of a material with uniform strain characteristics, the crank arm is adapted to be deformed by a force, the thin material layer is adapted to be deformed correspondingly with the deformation of the crank arm, the at least one sensing element is adapted to measure the corresponding strain of the thin material layer to measure the force applied on the crank arm. A bicycle and a stationary exercise bicycle equipped with the crank apparatus are further provided.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Applicant: Giant Manufacturing Co., Ltd.
    Inventors: Chung-Wei Lin, Hsaio-Wen Hsu, Chih-Hsiang Shen, Ching-Yao Lin