Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: A camera module includes a metal yoke, a holding base, a plastic barrel, a plurality of plastic lens elements, a leaf spring pair and a coil element. The holding base is connected to the metal yoke and defines an inner space. The holding base has a through hole which is corresponding to an opening of the metal yoke. The plastic barrel is movably disposed in the inner space. The plastic lens elements are disposed in the plastic barrel. The leaf spring pair includes two leaf springs which are located on a same plane and connected to the plastic barrel. The coil element surrounds an outer surface of the plastic barrel and electrically connected to the leaf spring pair, wherein two ends of the coil element is connected to the leaf springs by a thermal pressing method.

Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

Abstract: A method for assessing the risk of cutaneous adverse drug reactions (CADRs) caused by an epidermal growth factor receptor inhibitor is provided, wherein the CADRs comprises but not limited to: maculopapular eruption (MPE), erythema multiforme (EM), Stevens Johnson syndrome (SJS), toxic epidermal necrolysis (TEN), and drug rash with eosinophilia and systemic symptoms (DRESS). Also provided is a detection kit for assessing the risk of developing CADRs in patients, said kit comprising a reagent for determining specific HLA alleles and a use of the detection kit in assessing the risk of developing CADR in a patient.

Abstract: A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells. The multiple SRAM cells are configured to form a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input.

Abstract: An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

Abstract: A hot-swap circuit for providing soft start and overcurrent protection to an electronic circuit may include a controller and a timer. The controller may be configured to sense an electrical current associated with the hot-swap circuit, based on the electrical current sensed, perform current limiting of the electrical current to minimize inrush current to the electronic circuit, and disable the electrical current from flowing to the electronic circuit in response to the electrical current exceeding an overcurrent threshold for longer than a duration of a fault timer. The timer circuit may be configured to, for a period of time after enabling of the hot-swap circuit, cause the duration of the fault timer to be a first duration, and after the period of time, cause the duration of the fault timer to be a second duration significantly shorter than the first duration.

Abstract: A multi-modal image alignment method includes obtaining first points corresponding to a center vertex of a calibration object and second point groups corresponding to side vertices of the calibration object from two-dimensional images, obtaining third points corresponding to the center vertex from three-dimensional images, performing first optimizing computation using a first coordinate system associated with the two-dimensional images, the first points and the third points to obtain a first transformation matrix, processing on the three-dimensional images using the first transformation matrix to generate firstly-transformed images respectively, performing second optimizing computation using the firstly-transformed images, the first points and the second point groups to obtain a second transformation matrix, and transforming an image to be processed from a second coordinate system associated with the three-dimensional images to the first coordinate system using the first transformation matrix and the second t

Abstract: A circuit board includes multiple of first touch sensing electrodes, multiple of second touch sensing electrodes, and multiple of dummy patterns. The first touch sensing electrodes extend along a first direction. The second touch sensing electrodes extend along a second direction. The first touch sensing electrodes are electrically insulated from the second touch sensing electrodes. The first direction is not parallel to the second direction. The dummy patterns are positioned on the areas between the first touch sensing electrodes and the second touch sensing electrodes. The first touch sensing electrodes, the second touch sensing electrodes, and the dummy electrodes are non-transparent.

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

Abstract: An imaging lens driving module includes a lens carrier, a frame element, a driving mechanism and a metal conductive element. The lens carrier is disposed in the frame element. The driving mechanism includes a metal elastic element, a coil and a magnet assembly. The metal elastic element includes an outer fixing part coupled to the frame element, an inner fixing part coupled to the lens carrier, and an elastic part. The coil is fixed to the lens carrier and disposed corresponding to the magnet assembly. The metal conductive element is coupled to the lens carrier. The metal elastic element further includes an electrically connecting part and a compensating elastic part. The metal conductive element has a corresponsive surface corresponding to and electrically connected to the electrically connecting part. The compensating elastic part is connected to the electrically connecting part and the inner fixing part.

Abstract: This disclosure relates to a thin pump including a case, a rotor, and a stator. The case has a bottom surface, a lower chamber, an upper chamber, and an accommodation space. The upper chamber is located further away from the bottom surface than the lower chamber. The upper chamber has two opposite ends respectively in fluid communication with the lower chamber and the accommodation space. The rotor includes an impeller and a magnet. The impeller is rotatably disposed in the lower chamber of the case. The magnet is disposed on the impeller. The stator is disposed in the case. The stator corresponds to the magnet of the rotor so as to drive the rotor to rotate with respect to the case.

Abstract: A driving circuit includes at least one light-emitting element, a drive line, a data line, a touch sensor, and a read line. The drive line is electrically coupled to a first terminal of the at least one light-emitting element. The data line is electrically coupled to a second terminal of the at least one light-emitting element. The drive line is electrically coupled to a first terminal of the touch sensor. The read line is electrically coupled to a second terminal of the touch sensor. The read line is electrically isolated from the data line.

Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

Abstract: A tool connector is provided, including: a rod, a sliding sleeve, a locking member, a push rod, a sliding rod, a first elastic member and a second elastic member. The sliding sleeve is movably sleeved to the rod. The sliding rod is disposed through the push rod and slidably disposed on the rod. The sliding rod is comovable with the push rod. The first elastic member is elastically abutted against and between the push rod and the rod. The second elastic member is elastically abutted against and between the rod and the sliding sleeve.