Patents by Inventor Wen Hung (Steven) Lu

Wen Hung (Steven) Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nanowire transistor and method for fabricating the same
    Patent number: 11705498
    Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kuang Hsieh, Shih-Hung Tsai, Ching-Wen Hung, Chun-Hsien Lin
  • Camera module having reflective element and electronic device
    Patent number: 11703658
    Abstract: A camera module includes a base, a lens module, a reflection module, a longitudinal guiding bar, a transverse guiding bar and a shaft guiding bar. The lens module has an optical axis and is disposed on the base. The reflection module includes a reflective element disposed on the base and located on an object side of the lens module. The longitudinal and transverse guiding bars are disposed between the base and the lens module and respectively extend in a first direction parallel to the optical axis and a second direction perpendicular to the optical axis. The shaft guiding bar is disposed between the base and the reflection module and extends in the second direction. The lens module is movable along the longitudinal and transverse guiding bars, respectively, and the reflective element is rotatable by taking the shaft guiding bar as a rotation axis.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: July 18, 2023
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Lin An Chang, Ming-Ta Chou, Wen-Hung Hsu, Te-Sheng Tseng
  • SEMICONDUCTOR DEVICE WITH NON-CONFORMAL GATE DIELETRIC LAYERS
    Publication number: 20230215766
    Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Yung-Hsiang Chan, Wen-Hung Huang, Shan-Mei Liao, Jian-Hao Chen, Kuo-Feng Yu, Kuei-Lun Lin
  • QUANTUM CIRCUIT WITH TRENCH CAPACITOR
    Publication number: 20230210024
    Abstract: One or more systems, devices, methods of use and/or methods of fabrication provided herein relate to a superconducting device that can be operated with minimal electric field energy coupling at surface layers of the superconducting device and/or that can have a small footprint. According to one embodiment, a device can comprise a Josephson junction located between a first capacitor portion and a second capacitor portion of a capacitor, wherein at least a trenched section of the first capacitor portion is located beneath a surface of a substrate, and wherein at least a trenched section of the second capacitor portion is located beneath the surface of the substrate. According to another embodiment, a device can comprise a capacitor disposed within a substrate layer and the capacitor comprising a pair of material-filled trenches in the substrate layer, and a Josephson junction coupled to the capacitor.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Inventors: Li-Wen Hung, Elbert Emin Huang, Harry Jonathon Mamin, Daniel Rugar, Martin O. Sandberg, Joseph Finley
  • Driving circuit and driving method
    Patent number: 11687202
    Abstract: A driving circuit includes at least one light-emitting element, a drive line, a data line, a touch sensor, and a read line. The drive line is electrically coupled to a first terminal of the at least one light-emitting element. The data line is electrically coupled to a second terminal of the at least one light-emitting element. The drive line is electrically coupled to a first terminal of the touch sensor. The read line is electrically coupled to a second terminal of the touch sensor. The read line is electrically isolated from the data line.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: June 27, 2023
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Ming-Chuan Lin, Wen-Hung Wang, Chuan-Chih Fu
  • INTEGRATED ANTENNA PACKAGE STRUCTURE
    Publication number: 20230197680
    Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 22, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Po-Kai Chiu, Sheng-Tsai Wu, Yu-Min Lin, Wen-Hung Liu, Ang-Ying Lin, Chang-Sheng Chen
  • FIBER COMPOSITE MATERIAL AND METHOD FOR PRODUCING THE SAME
    Publication number: 20230192541
    Abstract: The present invention relates to a fiber composite material and a method for producing the fiber composite material. The method for producing the fiber composite material includes a hydrolysis step of a silicon precursor having an alkoxy group, an in-situ condensation step and a drying step. A specific silicon precursor having a secondary amino group and alkyl groups is used therein, as well as a specific weight ratio of the silicon precursor to a fiber material, the in-situ condensation step can be performed in the absence of organic solvents in the method for producing the fiber composite material, and a hydrophobic modification on silicon-based gels can be performed, thereby simplifying the process, decreasing a thermal conductivity of the resulted fiber composite material and preventing drop dust of the resulted fiber composite material.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: Wen-Bee KUO, Ming-Hung CHENG, Wan-Tun HUNG, Yu-Cheng CHEN, Wen-Hung TSENG, Kuo-Ming HUANG, Wen-Chieh LAI, Shang-Shih LI, Wen-Yuan CHEN, Hsin TSENG, Hsun-Ku LEE, Yu-Hsin CHEN
  • SILICON-BASED POWDERS AND METHOD FOR PRODUCING THE SAME
    Publication number: 20230192501
    Abstract: The present invention relates to silicon-based powders and a method for producing the silicon-based powders. The method for producing the silicon-based powders includes a hydrolysis step of a silicon precursor having an alkoxy group, a condensation step and a drying step. By a specific weight ratio of water to the silicon precursor having the alkoxy group and a silicon precursor having a secondary amino group and an alkyl group, in the method for producing the silicon-based powders, the condensation step can be performed without organic solvents, and a modification on silicon-based gels can be performed to enhance a safety of processes and a hydrophobicity of the resulted silicon-based powders, and decrease a thermal conductivity and a bulk density of the resulted silicon-based powders.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 22, 2023
    Inventors: Wen-Bee KUO, Ming-Hung CHENG, Wan-Tun HUNG, Yu-Cheng CHEN, Wen-Hung TSENG, Kuo-Ming HUANG, Wen-Chieh LAI, Shang-Shih LI, Wen-Yuan CHEN, Hsin TSENG, Hsun-Ku LEE, Yu-Hsin CHEN
  • Lens assembly driving module, photographing system and cell phone device
    Patent number: 11681117
    Abstract: A lens assembly driving module includes a holder, a metal yoke, a lens unit, a magnet set, a coil, at least one elastic element and at least one damper agent. The metal yoke is coupled with the holder and includes a through hole and at least one extending structure. The extending structure is disposed around the through hole and extends along a direction from the through hole to the holder. The lens unit is movably disposed in the metal yoke. The lens unit includes an optical axis and at least one notch structure. The notch structure is disposed in an outer peripheral area of the lens unit and is corresponding to the extending structure. The damper agent is disposed between the extending structure of the metal yoke and the notch structure of the lens unit. The damper agent is applied to damp a movement of the lens unit.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: June 20, 2023
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Chun-Yi Lu, Te-Sheng Tseng, Wen-Hung Hsu, Ming-Ta Chou
  • DIELECTRIC SIDEWALL PROTECTION AND SEALING FOR SEMICONDUCTOR DEVICES IN A IN WAFER LEVEL PACKAGING PROCESS
    Publication number: 20230187299
    Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Kuan-Hsiang Mao, Che Ming Fang, Yufu Liu, Wen Hung Huang
  • BACKSIDE AND SIDEWALL METALLIZATION OF SEMICONDUCTOR DEVICES
    Publication number: 20230187211
    Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Kuan-Hsiang Mao, Wen Hung Huang, Che Ming Fang, Yufu Liu
  • Adaptive short circuit detection system and method for an information handling system (IHS)
    Patent number: 11668761
    Abstract: Embodiments of systems and methods for detecting short circuits in a load are described. In an illustrative, non-limiting embodiment, a short circuit detection system includes a first circuit, a second circuit, and a controller. The first circuit has an output and an input coupled to a load and an auxiliary power source through a resistor, while the second circuit is configured to enable an output of the short circuit detection circuit for a specified period of time following application of auxiliary power at the auxiliary power source. The controller includes computer-executable instructions to monitor the output of the first circuit, and allow or disallow a main power source from powering the load based upon whether a short circuit condition exists.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: June 6, 2023
    Assignee: Dell Products, L.P.
    Inventors: Lei Wang, Wen-Hung Huang, Guangyong Zhu, Jaehyeung Park
  • Lens assembly actuating module and electronic device
    Patent number: 11668895
    Abstract: A lens assembly actuating module includes a holder, a metal yoke, a lens actuator and a Hall sensor. The holder includes a central opening, at least three metal connectors insert-molded with the holder, at least two metal terminals insert-molded with the holder, and a plurality of plated metal layers disposed on a surface of the holder. The metal yoke is coupled with the holder. The lens actuator is for carrying a lens unit including an optical axis. The lens actuator is movably disposed in the metal yoke. The lens actuator includes at least one elastic element and at least three metal hanging wires. The Hall sensor is disposed on one of the plated metal layers of the holder. The Hall sensor is for detecting a movement of the lens unit along a direction perpendicular to the optical axis.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: June 6, 2023
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Te-Sheng Tseng, Wen-Hung Hsu, Ming-Ta Chou
  • Multiple threshold voltage implementation through lanthanum incorporation
    Patent number: 11664279
    Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Shan-Mei Liao, Jer-Fu Wang, Yung-Hsiang Chan
  • Light-emitting device
    Patent number: 11658269
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 23, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Decision feedback equalization embedded in slicer
    Patent number: 11652673
    Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Chun Yang, Wen-Hung Huang
  • Pre-resist island forming via method and apparatus
    Patent number: 11640947
    Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 2, 2023
    Assignee: NXP B.V.
    Inventors: Kuan-Hsiang Mao, Wen Hung Huang, Che Ming Fang, Yufu Liu
  • INFERENCE FOCUS FOR OFFLINE TRAINING OF SRAM INFERENCE ENGINE IN BINARY NEURAL NETWORK
    Publication number: 20230121677
    Abstract: A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells forming a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input. The SRAM computation architecture is configured to store ternary data and perform local computations on the ternary data.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventors: Chia-Yu Chen, Jui-Hsin Lai, Ko-Tao Lee, Li-Wen Hung
  • Wafer holding pins and methods of using the same
    Patent number: 11626300
    Abstract: An apparatus includes a substrate stage configured to secure a substrate thereon and a motion mechanism configured to rotate the substrate stage. The substrate stage includes a plurality of holding pins for holding an edge of the substrate. Rotating the substrate stage causes a chemical solution dispensed on an upper surface of the substrate to spread outwardly toward the edge of the substrate. At least one of the plurality of holding pins includes at least one opening or at least one tapered side surface, or both, for guiding the chemical solution to flow off the substrate.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Lun Chen, Ming-Sung Hung, Po-Jen Shih, Wen-Hung Hsu
  • ADAPTIVE SHORT CIRCUIT DETECTION SYSTEM AND METHOD FOR AN INFORMATION HANDLING SYSTEM (IHS)
    Publication number: 20230104077
    Abstract: Embodiments of systems and methods for detecting short circuits in a load are described. In an illustrative, non-limiting embodiment, a short circuit detection system includes a first circuit, a second circuit, and a controller. The first circuit has an output and an input coupled to a load and an auxiliary power source through a resistor, while the second circuit is configured to enable an output of the short circuit detection circuit for a specified period of time following application of auxiliary power at the auxiliary power source. The controller includes computer-executable instructions to monitor the output of the first circuit, and allow or disallow a main power source from powering the load based upon whether a short circuit condition exists.
    Type: Application
    Filed: October 6, 2021
    Publication date: April 6, 2023
    Applicant: Dell Products, L.P.
    Inventors: Lei Wang, Wen-Hung Huang, Guangyong Zhu, Jaehyeung Park