Abstract: A semiconductor device package includes a semiconductor device and an electrically conductive pad disposed in contact with a surface of the semiconductor device. The semiconductor device package further includes a redistribution layer (RDL) formed over the electrically conductive pad and the surface of the semiconductor device, and an electrical connector disposed over and electrically coupled to the RDL. The RDL includes a first passivation layer disposed over a surface of the semiconductor device and the electrically conductive pad, and further includes an RDL trace. The RDL trace includes a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion having a non-planar and undulating configuration relative to the surface of the semiconductor device.

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

Abstract: An integrated circuit (IC) package includes one or more microelectronic devices disposed between a first side and an opposing second side of the IC package and further includes a metal frame structure comprising a metal layer disposed at the second side, an embedded ground plane (EGP) structure encircling the one or more microelectronic devices, and a set of stacked conductive structures extending from the EGP structure to the first side through a set of one or more redistribution layers at the first side. The IC package further can include an array of package contacts disposed at the first side and an encapsulant layer encapsulating the one or more microelectronic devices in a volume defined by an inner sidewall of the EGP structure.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.

Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

Abstract: The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.

Abstract: A leak inhibition/detection device includes an absorbent material, a leak sensor in contact with the absorbent material, and an enclosure surrounding the absorbent material. The leak inhibition/detection device is configured to surround a joint between tubing and a cold plate/evaporator or a radiator/condenser of a liquid cooling module of an information handling system.

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

Abstract: A camera module includes a metal yoke, a holder, a plastic barrel, a plurality of plastic lens elements and a plurality of metal conducting elements. The holder is connected to the metal yoke for forming an inner space. The plastic barrel is movably disposed in the inner space and includes at least one buffering part. The plastic lens elements are disposed in the plastic barrel. The metal conducting elements are at least one leaf spring and a wire element, wherein the metal conducting elements are connected to the plastic barrel. Before the at least one buffering part contacts a contacting part of the at least one leaf spring, there is a gap distance between the at least one buffering part and the contacting part of the at least one leaf spring.

Abstract: A Static Random Access Memory (SRAM) device in a binary neural network is provided. The SRAM device includes an SRAM inference engine having an SRAM computation architecture with a forward path that include multiple SRAM cells forming a chain of SRAM cells such that an output of a given one of the multiple SRAM cells is an input to a following one of the multiple SRAM cells. The SRAM computation architecture is configured to compute a prediction from an input. The SRAM computation architecture is configured to store ternary data and perform local computations on the ternary data.

Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a first edge; a reflective structure located on the second semiconductor layer and including an outer edge; a first electrode pad located on the reflective structure, wherein the first electrode pad including an outer side wall adjacent to the outer edge, wherein the outer edge extends beyond the outer side wall and does not exceed the first edge in a cross-sectional view of the light-emitting device.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: Five-side mold protection for semiconductor packages is described. In an illustrative, non-limiting embodiment, a semiconductor package may include: a substrate comprising a top surface, a bottom surface, and four sidewalls; an electrical component comprising a backside and a frontside, where the frontside of the electrical component is coupled to the top surface of the substrate; and a molding compound, where the molding compound encapsulates the backside of the electrical component and the four sidewalls of the substrate.

Abstract: A tool connector is provided, including: a main body, including a connection portion including a through hole, a blocking member being movably received in the through hole; an adapter member, inserted in the main body and movable between first and second positions, wherein when located in the first position, the adapter member is abutted against the blocking member so that the blocking member is urged outwardly, when the adapter member is located in the second position, the blocking member is not urged outwardly by the adapter member so that the blocking member is inwardly movable, and the adapter member further includes a connection hole; an elastic member, disposed between the main body and the adapter member, urging the adapter member toward the first position; at least one detent member, disposed on the main body, configured to block the adapter member from detaching from the main body.

Abstract: A tool connector is provided, including: a main body, including a connection portion including a through hole, a blocking member being movably received in the through hole; an adapter member, inserted in the main body and movable between a first position and a second position, wherein when the adapter member is located in the first position, the adapter member is abutted radially against the blocking member so that the blocking member is urged outwardly, and when the adapter member is located in the second position, the blocking member is not urged outwardly by the adapter member so that the blocking member is inwardly movable; an elastic member, disposed between the main body and the adapter member, urging the adapter member toward the first position; at least one detent member, disposed on the main body, configured to block the adapter member from detaching from the main body.