Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: The present invention relates to methods for treating dermatitis and the use of a ?-1 adrenoceptor antagonist in manufacturing a pharmaceutical composition for treating dermatitis. The methods comprise the step of administering the pharmaceutical composition comprising a therapeutically effective amount of ?-1 adrenoceptor antagonist to a subject in need thereof.

Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes a lateral outer perimeter surface surrounding the active layer; a plurality of vias penetrating the semiconductor stack to expose the first semiconductor layer; a first pad portion and a second pad portion formed on the semiconductor stack to respectively electrically connected to the first semiconductor layer and the second semiconductor layer, wherein the second pad portion and the first pad portion are arranged in a first direction; wherein the plurality of vias is arranged in a plurality of rows, the plurality of rows are arranged in the first direction and includes a first row and a second row, the first row is covered by the second pad portion, the second row is not covered by the first pad portion and the second pad portion, whe

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Abstract: A thermal imaging apparatus for measuring a temperature of a target in a monitored area comprises a thermal imager, an optical image capturing device and a computing processing device. The thermal imager is configured to capture a thermal image of the monitored area. The optical image capturing device is configured to capture optical images of the monitored area. The computing processing device is configured to determine one of the optical images as a determined optical image synchronizing with the thermal image according to positions of blocks corresponding to the target in the thermal image and the optical images, perform calculation according to the thermal image and the determined optical image to obtain a measured distance between the target and the thermal imaging apparatus, and perform calibration according to the measured distance and the thermal image to obtain a calibrated temperature value of the target.

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: An antenna board alignment method includes following steps: A microprocessor finds a central positioning point on an antenna board to locate a positioning rectangle. The microprocessor finds four inner positioning points on the positioning rectangle to locate the antenna board. The microprocessor finds a plurality of outer positioning points at a plurality of edge locations on the antenna board to locate at least one edge of the antenna board.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.

Abstract: The present invention relates to the use of ?-1 adrenergic receptor antagonist to prepare compositions for reducing or preventing damage to normal epithelial cells induced by epidermal growth factor receptor inhibitor (EGFRI) and inhibiting cancer cells, by administering a composition containing a ?-1 adrenergic receptor antagonist to reduce damage to normal epithelial cells induced by the EGFRI. The composition comprising ?-1 adrenergic receptor antagonist is administered to reduce damage to normal epithelial cells induced by the EGFRI. The composition comprising ?-1 adrenergic receptor antagonist can be administered together with an epidermal growth factor receptor inhibitor to synergistically inhibit cancer cells.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a first edge; a reflective structure located on the second semiconductor layer and including an outer edge; a first electrode pad located on the reflective structure, wherein the first electrode pad including an outer side wall adjacent to the outer edge, wherein the outer edge extends beyond the outer side wall and does not exceed the first edge in a cross-sectional view of the light-emitting device.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A manufacturing method of a semiconductor device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A transistor is formed on a substrate. The transistor includes a plurality of semiconductor sheets and two source/drain structures. The semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two source/drain structures are disposed at two opposite sides of each of the semiconductor sheets in a horizontal direction respectively, and the two source/drain structures are connected with the semiconductor sheets.

Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

Abstract: A torsion sensor, including a casing assembly, a sleeve set, a driven slider, a driving slider, an elastic member, a magnetic sensor, and a magnetic member is provided. The sleeve set includes a first sleeve, a second sleeve, and a third sleeve. The first sleeve is disposed in the casing assembly. The second sleeve has a neck portion sleeved on the second side of the first sleeve. The third sleeve is disposed between the first and the second sleeves. The driven slider is connected to a head portion of the second sleeve. The driving slider surrounds an outer side of the driven slider. The elastic member surrounds an outer side of the second sleeve. One of the magnetic sensor and the magnetic member is disposed in the casing assembly, and the other one is disposed in the sleeve set. The magnetic sensor and the magnetic member are disposed opposite to each other.

Abstract: An electronic device, including a circuit board and a back plate, is provided. The circuit board has a first opening. The back plate includes a bottom portion, a protruding portion, and a column. The protruding portion protrudes from the bottom portion, and the column is located on the protruding portion. In a first direction, the column has a first outer diameter and a second outer diameter. A first width of the first opening is less than the first outer diameter and greater than the second outer diameter to limit the movement of the circuit board. The electronic device of the disclosure limits the movement of the circuit board through the column of the back plate, so as to reduce the number of screws used, thereby achieving the effects of reducing costs and/or reducing man-hours for locking the screws.

Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.