Abstract: A semiconductor packaging structure. The structure comprises a chip, a lead frame, and a plurality of wires. The chip comprises an active surface and an opposing non-active surface, the active surface comprising a central area and a peripheral area having a plurality of bonding pads. The lead frame comprises a plurality of the leads, a plurality of tie bars, and a chip paddle. The tie bars is connected with the chip paddle and attached to the active surface of the chip in such a way as to avoid contact with the bonding pads. As well, the wires electrically connect with the bonding pad and the leads.

Abstract: A magnetic memory device and the method for making same are disclosed. The device uses two metal lines to control a combined magnetic field created thereof. The device has a magnetic memory element connecting to a substrate at a first end thereof, a first metal line connecting to a second end of the magnetic memory element. Further, the device has a second metal line crossing perpendicularly over the first metal line for jointly generating the combined magnetic field, wherein the second metal line is on the side of the second end of the magnetic memory element.

Abstract: The present invention relates to a system and an device for calibrating oscillator characteristic curve, more particularly, to a system and device that are capable of making an evaluation to determine whether it is necessary to change the characteristic curve of the oscillator by means of a calibration device; if so, the device will send a calibration signal to a calibration circuit for changing the circuit characteristic thereof so as to choose an appropriate characteristic curve of the oscillator. The present invention can calibrate the frequency characteristic curve of the oscillator automatically so as to avoid being affected by the manufacture process and temperature. Furthermore, the manual adjustment is no longer required before every shipping that not only can reduce the uncertainty caused by manual adjustment, but also can reduce labor cost.

Abstract: A dual chips stacked packaging structure. A first chip comprises an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads. A lead frame comprises a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, with the first adhering surface adhering to the active surface of the first chip in such a way as to avoid contact with the first bonding pads. A second chip comprises an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, and the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads. Parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.

Abstract: A signal transmission cable is disclosed. The cable comprises a plurality of connectors and a cable unit wherein these connectors are coupled with each other by the cable unit. These connectors of the cable in parallel connection are respectively connected to connectors of a computer host of a PC. Therefore, one other connector of the cable could provide a few times the quantity of electric current supplied by each of the connectors of the computer host so that the cable could provide enough drive current to an extended peripheral like an extended optical disk drive.

Abstract: A higher frequency clock and a lower frequency clock are locked at a predetermined phase relationship. A total number of pulses of the higher frequency clock occurring between two sequential rising edges of the lower frequency are calculated. A count start signal is generated in response to a rising edge of the lower frequency clock. A value of a lower frequency clock count is set in response to the count start signal. The value of the lower frequency clock decrements in accordance with a frequency of the higher frequency clock. When the value of the lower frequency clock has decreased by the total number of pulses of the higher frequency clock occurring between two consecutive rising edges of the lower frequency minus 1, a synchronization signal is generated for indicating occurrence of the predetermined phase relationship between the higher frequency clock and the lower frequency clock.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: An atomizing apparatus for the production of powders or spray deposits, having an atomization device for receiving a liquid stream of molten metal or metal alloy to be atomized; at least two primary atomization gas jets for directing an atomization gas at an angle into the liquid stream in an atomization zone at an impinging point of the atomization jets to break the stream into atomized droplets; and at least two secondary jets for direction a controlling fluid at a pressure, flow rate and direction, the jets being aimed at the atomization gas jet or into the atomization zone, wherein said secondary jets control a backpressure generated by the primary atomization gas jets. The apparatus also includes means for in-situ controlling at least one of the relative positions among the primary atomization jets, the secondary jets, and the liquid delivery nozzle.

Abstract: A wrench includes a handle, a head having a pivotal portion, and a retaining mechanism for retaining the head in the desired angular position relative to the handle. The pivotal portion of the head includes a fore lug and a rear lug that are located with reference to a ratcheting direction of the handle. The handle has an engaging portion pivotally received in an opening between the lugs. Teeth are defined in an arcuate outer surface section of the fore lug. The thickness of the rear lug is not reduced, avoiding damage to the torque-bearing section in the pin hole of the rear lug.

Abstract: A method for fabricating a microelectronic product provides for forming a planarizing layer upon a bond pad and a topographic feature, both formed laterally separated over a substrate. The planarizing layer is formed with a diminished thickness upon the bond pad such that it may be readily etched to expose the bond pad while employing as a mask an additional layer formed over the topographic feature but not over the bond pad. The method is particularly useful for forming color filter sensor image array optoelectronic products with attenuated bond pad corrosion.

Abstract: A spinal implant of cortical bone for insertion in the anterior to antereolateral approaches has a smooth surfaced cylindrical bore along a plane between inferior and superior vertebral engagement surfaces which may be roughened and which may be inclined to match the lordosis of the vertebrae. The bore may extend from the anterior surface through the implant into a central chamber or may be blind. The instrument has a straight shaft which is bent at a proximal end opposite a handle at the distal end. The bend is formed into an implant engaging member which has a circular cylindrical smooth surface and closely mates with and is complementary to the implant bore. The instrument is used to rotate or otherwise finely manipulate the implant in the plane of the disc space to a desired orientation from the initial improper insertion orientation.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: Methods and systems for providing a video stream from a server to a client over a network include a memory for storing a forward-encoded bit-stream and a reverse-encoded bit-stream for a video data. The forward-encoded bit-stream includes I-frames encoded without inter-frame dependencies and P-frames encoded depending on forward-direction preceding frames, and the reverse-encoded bit-stream includes I-frames and P-frames encoded depending on reverse-direction preceding frames. When the server receives a request with a video cassette recording (VCR) function from the client, the server reads out and transmits frames selectively from among the first, second, third, and fourth frames in accordance with the request. The server can select the closest I-frame to a requested frame in either bit-stream for a fast-mode play or a random-access play, and switch the bit-streams to use subsequent P-frames in a different direction than that of the closest I-frame.

Abstract: A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test pattern stored in the first memory is hardware-simulated. If an external interrupt is received during the simulation of the test pattern, the second memory region is accessed and the interrupt instructions are hardware-simulated. Thereafter, the simulated result of the interrupt instructions is self-tested to obtain a first verification result, and the hardware design is verified according to the first verification result.

Abstract: A dowel insertion tool includes a T-shaped handle and a hollow sleeve which extends distally from the T-shaped handle. A shaft extends from the handle through the hollow sleeve and includes a transverse extension. A rotatable knob having an annular channel positioned to receive the transverse extension is supported adjacent the handle. A pin is secured to the knob and extends into a helical camming channel formed in the sleeve. Upon rotation of the knob, the pin moves within the camming channel to move the knob longitudinally about the sleeve. Movement of the knob effects longitudinal movement of the shaft. A support plate is secured to the distal end of the shaft. A pair of prongs are slidably secured to the plate. Each of the prongs includes an enlarged head portion which is slidably positioned within a slot formed in the plate. A guide member is secured to the distal end of the sleeve. The guide member includes a pair of guide bores dimensioned to receive a distal end of the prongs.

Abstract: A process for etching a metal layer. First, a semiconducting substrate having a metal layer and an anti-reflective layer thereon is provided. Next, the surface of the anti-reflective layer is treated with a weak base aqueous solution. Next, a photoresist layer is formed on the treated anti-reflective layer and then patterned. Next, the treated anti-reflective layer and metal layer are etched using the photoresist pattern as a mask. Finally, the photoresist pattern and anti-reflective layer are removed. The present invention prevents undercut and collapse of photoresist pattern, thus obtaining an accurate metal layer pattern.

Abstract: A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.

Abstract: In accordance with the present invention, an apparatus and a method for regulating exhaust pressure in an evacuation system of a semiconductor process chamber are provided. The method comprises steps of generating a first pressure in the semiconductor process chamber with the evacuation system, monitoring the first pressure to generate a first signal, determining a set point for the exhaust pressure responsive to the first signal, and regulating the exhaust pressure by a controller till reaching the set point. The key aspect of the present invention is to maintain the equilibrium of the chamber pressure and the exhaust pressure by implementing an exhaust controller to control the gas flow rate introduced into the evacuation system. In other words, when the chamber pressure is increased, the gas is introduced into the evacuation system at an increased flow rate. On the other hand, when the chamber pressure is decreased, the gas is introduced into the evacuation system at a decreased flow rate.

Abstract: A rain shoe connected with a rain outfit, particularly apply to bicycle and motorcycle riders in for preventing rain immersion, which mainly includes a pair of extension portions, connection portions, gaiters and at least one receiving device; wherein the extension portion is disposed at a bottom portion of a raincoat and the lower aspect thereof is sequentially jointed by the connection portion and the gaiter; therefore, when user wears the raincoat, his or her legs are completely covered for preventing rain immersion; when the user's legs need no cover, all the members of the present invention are received fixedly into the receiving device located at the lower aspect of the raincoat for facilitating the application.