Abstract: A ratcheting tool includes a handle and a head extending from the handle. The handle includes a compartment communicated with a hole of the head. A drive member is rotatably mounted in the hole of the head and includes teeth on an outer periphery thereof. A pawl is slidably mounted in the compartment of the handle. The pawl includes teeth on a side thereof for engaging with the teeth of the drive member. An anchor is mounted in the compartment of the head. An elastic element is attached between the pawl and the anchor for biasing the teeth of the pawl to engage with the teeth of the drive member. A protruded portion is integrally formed on a wall defining the compartment of the handle for positioning the anchor in place, thereby preventing the anchor from moving out of the compartment of the handle.

Abstract: A multipoint video conferencing system employs a transcoder with a dynamic sub-window skipping technique to enhance the visual quality of the participants of interest. The system firstly identifies the active conferees from the multiple incoming video streams by calculating the temporal and the spatial activities of the conferee sub-windows. The sub-windows of inactive participants are dropped and the saved bits are reallocated to the active sub-windows. Numerous motion vector composition schemes can be used to compose the unavailable motion vectors in the dropped frames due to limited bit-rates or frame-rates of the user clients in video transcoding. The present invention employs a pre-filtered activity-based forward dominant vector selection (PA-FDVS) scheme which provides accurate approximation of motion vectors with low computational cost and memory requirement.

Abstract: A stacking multi-chip device comprises a substrate having a recess, stud bumpers or conductive stud strips thereon. A low die has a back surface affixed in the recess or the substrate, and has a first active surface comprising a plurality of bonding pads. The bonding pads of the low die have a set of elongate conductors connected to the substrate. An upper die has a back surface and a second active surface comprising a plurality of bonding pads. The bonding pads of the upper die have a plurality of stud bumpers connected to the stud bumpers, conductive stud strips, or the substrate by the method of reflow or anti-tropic conductive film. The second active surface is faced towards said first active surface and is offset stacked atop the low die to expose all bonding pads.

Abstract: A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

Abstract: A semiconductor package body having a lead frame. The lead frame is electrically connected to a semiconductor chip via at least one bonding wire in the semiconductor package body. The lead frame has a die pedestal having a first surface and a second surface opposite each other, a base pad disposed outside the die pedestal, at least one connecting part providing a connection between the die pedestal and the base pad, and a plurality of leads. Each lead has an electrical connecting portion and a connecting foot portion, in which the electrical connecting portion is electrically connected to the semiconductor chip via the bonding wire, and the connecting foot portion is exposed to the exterior of the semiconductor package body, thereby providing enhanced heat dissipation.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

Abstract: An automatic umbrella holding device on a bicycle mainly includes a clamp holder, a main supporting post, a bottom clamping frame, etc.; wherein, the said bottom clamping frame is fixedly clamped to a predetermined position on a handle bar of a bicycle; the bottom end of the main supporting post is positioned onto the said bottom clamping frame; the said clamp holder has a fixed arm and a moveable clamping arm; one end portion of the said fixed arm or the moveable clamping arm for clamping an umbrella handle grip is disposed with a clamping jacket having arcuate clamping planes for increasing the clamping effect.

Abstract: A control device includes a relay device coupled to a processor device, a power device coupled to the processor device and the relay device for energizing the processor device and the relay device, and a load device coupled to the relay device. A device may further be used for supplying control signals to the processor device, in order to switch on and switch off the relay device. The relay device includes two transistors coupled to the processor device, and two coils coupled to the transistors, for being actuated by the processor device with less electric power consumed.

Abstract: The present invention provides methods of screening an agent for activity using teleosts. Methods of screening an agent for angiogenesis activity, toxic activity and an effect cell death activity in teleosts are provided. The invention further provides high throughput methods of screening agents in multi-well plates.

Abstract: A control device includes a relay device coupled to a processor device, a power device coupled to the processor device and the relay device for energizing the processor device and the relay device, and a load device coupled to the relay device. A device may further be used for supplying control signals to the processor device, in order to switch on and switch off the relay device. The relay device includes two transistors coupled to the processor device, and two coils coupled to the transistors, for being actuated by the processor device with less electric power consumed.

Abstract: A transcoder for transcoding digital video signals includes a decoder and an encoder. In the decoder, an end-of-block (EOB) position of an incoming block received by the decoder is determined and a discrete cosine transform (DCT) block type is determined based on the determined EOB position. A reduced number of DCT coefficients is computed in a subsequent inverse DCT computation based on the DCT block type. In the encoder, if the incoming block is intercoded, no DCT coefficients are computed after the EOB of the incoming blocks is performing a DCT. Further, in the encoder when the incoming block is intercoded, an algorithm is applied to predict which DCT coefficients may become zero after a subsequent quantization operation, and only DCT coefficients that may not become zero are computed in performing the DCT.

Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

Abstract: An intervertebral spacer formed of dense cancellous human or animal bone is provided. In one preferred embodiment, the intervertebral spacer includes at least one bore which is dimensioned to receive a plug formed from cortical bone tissue. The cortical bone plug provides increased mechanical strength to the intervertebral spacer. Instrumentation for gauging the size of an intervertebral receiving bed and for grasping and inserting an intervertebral spacer or implant into an intervertebral receiving bed are also provided. These instruments include a spacer trial or set of spacer trials for determining the appropriate size spacer required for a particular surgical procedure, a spacer introducer for grasping and positioning a spacer at least partially within a receiving bed formed in the intervertebral space, and a bone tamp for driving a spacer into the receiving bed. Any one or all of these instruments may be provided in a kit for inserting an implant into the intervertebral space.

Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

Abstract: A fixing base for a card reader is built in a read and write apparatus frame in a personal computer to be in company with a mobile memory card reader. The mobile memory card is further associated with a USB to perform a function of detachable hot insertion and multiple node series so as to design an application of circuit connection and a composite structure.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

Abstract: An on-line Sagnac interferometric distributed fiber-optic leakage detection device comprising a light generator, an optical fiber coupler, a hollow pipeline, a Faraday rotator mirror, a sensing optical fiber, a delaying optical fiber, a photo detection device and a spectrum analyzer. Signals resulting from a leaky pipeline are obtained by the linear leakage detection system. The signals are analyzed by the spectrum analyzer to discover any null frequency shift so that exact location of the leakage point along the hollow pipeline can be computed.

Abstract: A block-based motion-compensated frame interpolation method and apparatus using a block-based video coder operating in low bit rates. Smooth movement of objects between video frames can be obtained without the complexity of pixel-wise interpolation motion estimation that is present in standard motion-compensated frame interpolation (MCI). An additional motion search for interpolating all of the individual pixel trajectories is not required because the interpolation uses block-based motion vector information from a standard codec such as H.26x/MPEG. Video quality is improved by increasing smoothness and the frame rate is increased without a substantial increase in the computational complexity. The proposed block-based MCI method maps from block-wise motion to pixel-wise motion in a motion vector mapping unit.

Abstract: A dielectric test structure formed over a dielectric layer. The test structure includes a first structure and a second structure. The first structure comprises a first liner pad, a second liner pad and a first conductive layer for connecting the first and the second liner pad. The second structure comprises a first section and a second section positioned symmetrically on each side of the first conductive layer but detached from the first conductive layer. The first section includes a second conductive layer parallel to the first conductive layer, a third liner pad and a third conductive layer for connecting the second conductive layer and the third liner pad. The second section includes a fourth conductive layer parallel to the first conductive layer, a fourth liner pad and a fifth conductive layer for connecting the fourth conductive layer and the fourth liner pad.