Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: The present application discloses a method for dynamic display of an application interface, including: parsing a configuration file of a first application to obtain a display string identifier of the first application; reading a display string of the first application from a resource file of the first application according to the display string identifier; and dynamically displaying the display string on the interface. The present invention also discloses an apparatus for dynamic display of an application interface. With the present invention, dynamic display of an application interface may be implemented.

Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.

Abstract: A method for using a bamboo leaf extract as an acrylamide inhibitor for heat processing food, includes adding to the bamboo leaf extract at least one selected from a group consisting of ginkgo extract, tea extract, rosemary extract, apple polyphenol extract, haw extract, onion extract, licorice extract, root of kudzuvine extract, grape seed extract and leech extract; and preparing a composition, in which the bamboo leaf extract takes up 34-95% of the total weight of the composition. The bamboo leaf extract used as the acrylamide inhibitor in food systems has an inhibiting rate to acrylamide formation of up to 15-98%.

Abstract: The present invention discloses a method, system and device for transmitting an E-DCH Random Access Uplink Control Channel (E-RUCCH), where the method includes: a UE judging whether a plurality of E-RUCCH transmission processes temporally overlap; and if there is overlapping, then the UE selecting and performing one of the E-RUCCH transmission processes and returning scheduling information and the identifier of the UE to a base station over an E-RUCCH. The method addresses the problem of coordination between E-RUCCH transmission processes triggered due to various reasons in a TD-SCDMA system with the enhanced feature of CELL_FACH introduced thereto.

Abstract: A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.

Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: Stereo image reconstruction techniques are described. An image from a root viewpoint is translated to an image from another viewpoint. Homography fitting is used to translate the image between viewpoints. Inverse compositional image alignment is used to determine a homography matrix and determine a pixel in the translated image.

Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

Abstract: A multifunctional optical film for enhancing light extraction includes a flexible substrate, a structured layer, and a backfill layer. The structured layer effectively uses microreplicated diffractive or scattering nanostructures located near enough to the light generation region to enable extraction of an evanescent wave from an organic light emitting diode (OLED) device. The backfill layer has a material having an index of refraction different from the index of refraction of the structured layer. The backfill layer also provides a planarizing layer over the structured layer in order to conform the light extraction film to a layer of an OLED lighting device such as solid state lighting devices or backlight units. The film may have additional layers added to or incorporated within it to an emissive surface in order to effect additional functionalities beyond improvement of light extraction efficiency.

Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

Abstract: Superhydrophobic films and methods of making such films are disclosed. More particularly, superhydrophobic films having durable nanostructures with high contrast ratios and various methods of producing such films are disclosed.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: This disclosure relates to a secure network device for multi-homed devices. An example network device includes a state table, an association establishment module, and an inspection module. The state table is configured to store information for communication associations between devices. The association establishment module is configured to process a request to establish a communication association between a first device and a second device and to store state information for the communication association in the state table. The first device and the second device each comprise a multi-homed device associated with a plurality of Internet Protocol (IP) addresses, and the state information includes the IP addresses associated with the first device and the IP addresses associated with the second device. The inspection module is configured to secure the communication association between the first device and the second device by using the state information that is stored in the state table.

Abstract: Method and apparatus for mitigating routing misbehavior in a network is described. In one example, routing protocol traffic is received from a remote router destined for a local router. The routing protocol traffic is parsed to identify a subset of traffic. The subset of traffic is normalized to identify and correct misconfigured routing updates. The routing protocol traffic is provided to the local router. In one embodiment, the subset of traffic is normalized by at least one of detecting and correcting routing protocol semantics, detecting and correcting violations in routing policies, detecting and correcting routing anomalies, or mitigating routing instability.

Abstract: Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

Abstract: A method for localized congestion exposure within a local loop in a cellular network that is performed by a localized congestion exposure receiver node of the local loop. The method includes receiving downlink packets destined for a downstream user device. The downlink packets have headers that indicate a level of congestion experienced by the downlink packets. The headers also indicate a level of expected downstream congestion declared by an upstream node. The method also includes forwarding the downlink packets to the downstream user device through a wireless connection. The method further includes sending packets upstream that have feedback indicative of the level of congestion experienced by the downlink packets and any congestion experienced within the localized congestion exposure receiver node.