Patents by Inventor Ying Zhang

Ying Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8124534
    Abstract: A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jin Wallner, Thomas A. Wallner, Ying Zhang
  • Patent number: 8115920
    Abstract: Provided is a method of making microarrays that includes providing a substrate with discrete first microfeatures that have a first profile, and depositing vapor-coated materials onto the first microfeatures to form second microfeatures having a second profile that is substantially different from the first profile. Also provided is a method of adding a replication material to the vapor-coated microfeatures to form a mold. Microarrays made by this method can be used as substrates for surface-enhanced Raman spectroscopy (SERS).
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: February 14, 2012
    Assignee: 3M Innovative Properties Company
    Inventors: Jun-Ying Zhang, Terry L. Smith, Haiyan Zhang, Jerome C. Porque, Ding Wang, John C. Hulteen, Lisa A. Dick
  • Publication number: 20120020533
    Abstract: A system and method for aligning maps using polyline matching is provided. A global map and a local map are represented as polyline maps including a plurality of line segments. One or more approximate matches between the polyline maps are identified. One or more refined matches are determined from the approximate matches. The global map and the local map are aligned at the one or more refined matches.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Juan Liu, Ying Zhang, Gabriel Hoffmann
  • Publication number: 20120012739
    Abstract: An optical device includes a light source (102), an optical microresonator (118) that supports at least a first optical guided mode (128) propagating along a first direction and at least a second optical guided mode (164) propagating along a second direction different from the first direction, and a detector (110,114). At least the first optical guided mode is excited by the emitted broadband light without the second optical guided mode being excited by the emitted broadband light. In some embodiments The detector receives and wavelength-averages light from the at least a second optical guided mode of the optical microresonator. In some embodiments, at least one of the light source, the microresonator and the detector is tunable.
    Type: Application
    Filed: December 17, 2009
    Publication date: January 19, 2012
    Inventors: Barry J. Koch, Terry L. Smith, Jun-Ying Zhang, Yasha Yi
  • Patent number: 8098150
    Abstract: One embodiment of the present invention provides a system that locates a set of target transmitting mechanism using a mobile sensing infrastructure. During operation, the system determines a reference frame of a sensing mechanism by detecting signals from at least two transmitting mechanisms. The system further determines locations of the target transmitting mechanism relative to the reference frame using the sensing mechanism. In addition, the system produces a result to indicate the locations of the target transmitting mechanisms.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: January 17, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Ying Zhang, James E. Reich
  • Publication number: 20110315950
    Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip, Sebastian U. Engelmann, Ying Zhang
  • Publication number: 20110317155
    Abstract: An apparatus for detecting electromagnetic waves includes a first electromagnetic wave sensor, two first electrodes, a second electromagnetic wave sensor, and two second electrodes. The two first electrodes are electrically connected to different portions of the first electromagnetic wave sensor. The second electromagnetic wave sensor crosses with and is spaced from the first electromagnetic wave sensor. The two second electrodes are electrically connected to different portions of the second electromagnetic wave sensor.
    Type: Application
    Filed: December 9, 2010
    Publication date: December 29, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: LIN XIAO, KAI-LI JIANG, YU-YING ZHANG, SHOU-SHAN FAN
  • Patent number: 8084825
    Abstract: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. Fuller, Timothy J. Dalton, Ying Zhang
  • Publication number: 20110311825
    Abstract: The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising: a. growing carbon nanotubes on a conductive substrate; b. filling the gap around the carbon nanotubes with a polymeric fill matrix comprising at least one latent photoacid generator; and c. selectively etching-back the polymeric fill matrix to expose tips of the carbon nanotubes.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Applicant: International Business Machines Corp.
    Inventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Ryan M. Martin, Ying Zhang
  • Publication number: 20110310017
    Abstract: A computer system includes a mouse and a computer for selecting a left-handed mode and a right-handed mode as a current operation mode of the mouse. When a right hand operates the mouse, the mouse automatically generates a first mode-setting signal, and the computer shifts the current operation mode to the right-handed mode according to the first mode-setting signal. When a left hand operates the mouse, the mouse automatically generates a second mode-setting signal different from the first mode-setting signal, and the computer shifts the current operation mode to the left-handed mode according to the second mode-setting signal.
    Type: Application
    Filed: September 24, 2010
    Publication date: December 22, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: ZHENG-HAO CHU, RUI-YING ZHANG
  • Publication number: 20110291188
    Abstract: A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Xuefeng Hua, Ying Zhang
  • Patent number: 8067110
    Abstract: A sorbent media protective device includes an enclosure having a gas inlet, gas outlet and a thin-film multilayer indicator. The thin-film multilayer indicator is proximate sorbent media that can sorb a vapor of interest flowing from the gas inlet towards the gas outlet. The indicator includes a porous detection layer whose optical thickness changes in the presence of the vapor, located between a semireflective layer and a reflective layer permeable to the vapor. With equilibration at the applied vapor concentration between at least a portion of the media and the vapor, the vapor can pass through the reflective layer into the detection layer and change the detection layer optical thickness sufficiently to cause a visibly discernible change in the indicator appearance if viewed through the semireflective layer.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: November 29, 2011
    Assignee: 3M Innovative Properties Company
    Inventors: Neal A. Rakow, James P. Mathers, Jun-Ying Zhang, Dora M. Paolucci, Richard J. Poirier, Moses M. David, John E. Trend, Michael S. Wendland
  • Publication number: 20110278580
    Abstract: A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Fuller, Steve Koester, Isaac Lauer, Ying Zhang
  • Publication number: 20110278672
    Abstract: A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Fuller, Steve Koester, Isaac Lauer, Ying Zhang
  • Publication number: 20110278673
    Abstract: A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Fuller, Steve Koester, Isaac Lauer, Ying Zhang
  • Publication number: 20110281068
    Abstract: A nanostructured article comprises a matrix and a nanoscale dispersed phase. The nanostructured article has a random nanostructured anisotropic surface.
    Type: Application
    Filed: December 18, 2009
    Publication date: November 17, 2011
    Inventors: Moses M. David, Andrew K. Hartzell, Timothy J. Hebrink, Ta-Hua Yu, Jun-Ying Zhang
  • Patent number: 8053809
    Abstract: A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric layer in the second region of the substrate. The semiconductor device may include a semiconductor body and a gate structure, in which the gate structure includes a gate dielectric material present on the semiconducting body and a metal gate material present on the gate dielectric material. The resistive structure may include semiconductor material having a lower surface is in direct contact with the dielectric layer in the second region of the substrate. The resistive structure may be a semiconductor containing fuse or a polysilicon resistor. A method of forming the aforementioned device is also provided.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Publication number: 20110267982
    Abstract: A system and method for determining an optimal backbone for a robotic relay network are provided. A robotic relay network comprising a plurality of nodes including a base station node, one or more mobile relay nodes, and one or more user nodes is provided. A signal strength value for each pair-wise communication link between each of the nodes is identified. A weight function is applied to each communication link value to determine a communication link weight. An optimal backbone tree is determined from the communication link weights.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ying Zhang, Gabe Hoffmann
  • Publication number: 20110263595
    Abstract: Compounds and salts thereof, formulations thereof, conjugates thereof, derivatives thereof, forms thereof and uses thereof are described. In certain aspects and embodiments, the described compounds or salts thereof, formulations thereof, conjugates thereof, derivatives thereof, forms thereof are active on one or more of Fms, Kit, Flt3, TrkA, TrkB and TrkC kinase protein.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 27, 2011
    Inventors: Jiazhong Zhang, Prabha N. Ibrahim, Wayne Spevak, James Tsai, Todd Ewing, Ying Zhang, Chao Zhang
  • Publication number: 20110261461
    Abstract: A light extraction film laminated to a glass substrate for organic light emitting diode (OLED) devices. The light extraction film includes a flexible substantially transparent film, a low index nanostructured layer applied to the film, and a high index planarizing backfill layer applied over the nanostructured layer. A glass substrate is laminated to the flexible substantially transparent film on a side opposite the nanostructured layer and including an ultra-low index region between the film and the glass substrate. The ultra-low index region is used to reduce optical losses occurring with the glass substrate.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 27, 2011
    Inventors: Ha T. Le, Jun-Ying Zhang, Sergey A. Lamansky, Scott M. Tapio, Encai Hao, David B. Stegall, Serena L. Mollenhauer