Patents by Inventor Ying Zhang

Ying Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiplying pattern density by single sidewall imaging transfer
    Patent number: 8354331
    Abstract: A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • METHOD FOR SELF ALIGNED METAL GATE CMOS
    Publication number: 20130012009
    Abstract: A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: International Business Machines Corporation (YT)
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS
    Publication number: 20130012025
    Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: KANGGUO CHENG, BRUCE B. DORIS, STEVEN J. HOLMES, XUEFENG HUA, YING ZHANG
  • METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS
    Publication number: 20130012026
    Abstract: A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Fuller, Steve Koester, Isaac Lauer, Ying Zhang
  • METHOD OF DRUG DELIVERY FOR PTH, PTHrP AND RELATED PEPTIDES
    Publication number: 20130006217
    Abstract: The present invention provides compositions, devices, methods and processes related to the intradermal delivery of PTHrP and PTHrP analogues, particularly [Glu22,25, Leu23,28,31, Aib29, Lys26,30]hPTHrP(1-34)NH2.
    Type: Application
    Filed: April 20, 2012
    Publication date: January 3, 2013
    Inventors: Gary Hattersley, Kris J. Hansen, Amy S. Determan, Ying Zhang
  • ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES
    Publication number: 20130001702
    Abstract: A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas formed in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Angle ion implant to re-shape sidewall image transfer patterns
    Patent number: 8343877
    Abstract: A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Method and apparatus for detecting polarizing direction of electromagnetic wave
    Patent number: 8334974
    Abstract: A method for detecting polarizing direction of electromagnetic wave includes disposing a carbon nanotube structure in a vacuum environment, irradiating a surface of the carbon nanotube structure by an electromagnetic wave with a polarizing direction while rotating the carbon nanotube structure, and determining the polarizing direction of the electromagnetic wave according to change of the visible light emitted from the carbon nanotube structure. The carbon nanotube structure includes a plurality of carbon nanotubes arranged along a substantially same direction. The carbon nanotube structure can absorb the electromagnetic wave and emit a visible light. The rotating axis is substantially perpendicular to the surface of the carbon nanotube structure irradiated by the electromagnetic wave.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: December 18, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Lin Xiao, Yu-Ying Zhang, Kai-Li Jiang, Liang Liu, Shou-Shan Fan
  • System and method for determining an optimal backbone for robotic relay networks
    Patent number: 8331267
    Abstract: A system and method for determining an optimal backbone for a robotic relay network are provided. A robotic relay network comprising a plurality of nodes including a base station node, one or more mobile relay nodes, and one or more user nodes is provided. A signal strength value for each pair-wise communication link between each of the nodes is identified. A weight function is applied to each communication link value to determine a communication link weight. An optimal backbone tree is determined from the communication link weights.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: December 11, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Ying Zhang, Gabriel Hoffmann
  • METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE REGIONS OF CMOS TRANSISTORS
    Publication number: 20120305928
    Abstract: A Field Effect Transistor (FET) device includes a gate stack formed over a channel region, a source region adjacent to the channel region, wherein a portion of a boundary between the source region and the channel region is defined along a plane defined by a sidewall of the gate stack, a drain region adjacent to the channel region, a portion of the drain region arranged below the gate stack, a native oxide layer disposed over a portion of the source region, along sidewalls of the gate stack, and over a portion of the drain region, a spacer arranged over a portion of the native oxide layer above the source region and the drain region and along the native oxide layer along the sidewalls of the gate stack.
    Type: Application
    Filed: August 2, 2012
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Fuller, Steve Koester, Isaac Lauer, Ying Zhang
  • NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE
    Publication number: 20120305886
    Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip, Sebastian U. Engelmann, Ying Zhang
  • CONTACTS FOR FET DEVICES
    Publication number: 20120306015
    Abstract: A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface.
    Type: Application
    Filed: July 31, 2012
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Keith Kwong Hon Wong, Ying Zhang
  • Contacts for FET devices
    Patent number: 8324058
    Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
    Type: Grant
    Filed: November 6, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Keith Kwong Hon Wong, Ying Zhang
  • Method of fabricating light extractor
    Patent number: 8324000
    Abstract: Methods of fabricating light extractors are disclosed. The method of fabricating an optical construction for extracting light from a substrate includes the steps of: (a) providing a substrate that has a surface; (b) disposing a plurality of structures on the surface of the substrate, where the plurality of structures form open areas that expose the surface of the substrate; (c) shrinking at least some of the structures; and (d) applying an overcoat to cover the shrunk structures and the surface of the substrate in the open areas.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: December 4, 2012
    Assignee: 3M Innovative Properties Company
    Inventors: Jun-Ying Zhang, Michael A. Haase, Terry L. Smith
  • Device having and method for forming fins with multiple widths for an integrated circuit
    Patent number: 8324036
    Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Steven J. Holmes, Xuefeng Hua, Ying Zhang
  • Enhancing MOSFET performance by optimizing stress properties
    Patent number: 8318570
    Abstract: A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • METHOD FOR SELF-ALIGNED METAL GATE CMOS
    Publication number: 20120292710
    Abstract: A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.
    Type: Application
    Filed: May 16, 2011
    Publication date: November 22, 2012
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • High Performance Drilling Fluids with Submicron-Size Particles as the Weighting Agent
    Publication number: 20120295821
    Abstract: Drilling fluids comprising a carrier fluid; a weighting agent that comprises sub-micron precipitated barite; a particle having a specific gravity of greater than about 2.6; and, a bridging agent that is not the submicron-precipitated barite or the particle. The weighting agent has a particle size distribution such that at least 10% of particles in the sub-micron precipitated barite have a diameter below about 0.2 microns, at least 50% of the particles in the sub-micron precipitated barite have a diameter below about 0.3 microns and at least 90% of the particles in the sub-micron precipitated barite have a diameter below about 0.5 microns. The particle has a specific gravity of greater than about 2.6 is not sub-micron precipitated barite. The ratio of the sub-micron precipitated barite to the particle is about 10:90 to about 99:1. The bridging agent comprises a degradable material.
    Type: Application
    Filed: June 27, 2012
    Publication date: November 22, 2012
    Applicant: Halliburton Energy Services, Inc.
    Inventor: Ying Zhang
  • High performance drilling fluids with submicron-size particles as the weighting agent
    Patent number: 8309497
    Abstract: Drilling fluids comprising a carrier fluid; a weighting agent that comprises sub-micron precipitated barite; a particle having a specific gravity of greater than about 2.6; and, a bridging agent that is not the submicron-precipitated barite or the particle. The weighting agent has a particle size distribution such that at least 10% of particles in the sub-micron precipitated barite have a diameter below about 0.2 microns, at least 50% of the particles in the sub-micron precipitated barite have a diameter below about 0.3 microns and at least 90% of the particles in the sub-micron precipitated barite have a diameter below about 0.5 microns. The particle has a specific gravity of greater than about 2.6 is not sub-micron precipitated barite. The ratio of the sub-micron precipitated barite to the particle is about 10:90 to about 99:1. The bridging agent comprises a degradable material.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: November 13, 2012
    Assignee: Halliburton Energy Services, Inc.
    Inventor: Ying Zhang
  • DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS
    Publication number: 20120280365
    Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Steven J. Holmes, Xuefeng Hua, Ying Zhang