Abstract: A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.

Abstract: Methods of fabricating light extractors are disclosed. The method of fabricating an optical construction for extracting light from a substrate includes the steps of: (a) providing a substrate that has a surface; (b) disposing a plurality of structures on the surface of the substrate, where the plurality of structures form open areas that expose the surface of the substrate; (c) shrinking at least some of the structures; and (d) applying an overcoat to cover the shrunk structures and the surface of the substrate in the open areas.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A process for etching semiconductors, such as II-VI or III-V semiconductors is provided. The method includes sputter etching the semiconductor through an etching mask using a nonreactive gas, removing the semiconductor and cleaning the chamber with a reactive gas. The etching mask includes a photoresist. Using this method, light-emitting diodes with light extracting elements or nano/micro-structures etched into the semiconductor material can be fabricated.

Abstract: A method is provided for anisotropically etching semiconductor materials such as II-VI and III-V semiconductors. The method involves repeated cycles of plasma sputter etching of semiconductor material with a non-reactive gas through an etch mask, followed by passivation of the side walls by plasma polymerization using a polymer former. Using this procedure small pixels in down-converted light-emitting diode devices can be fabricated.

Abstract: A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

Abstract: The disclosure provides a method of replicating a master using a patterned silicone daughter mold, from a master mold, the daughter mold having a layer of a ductile metal on the patterned surface thereof.

Abstract: Light converting constructions are disclosed. The light converting construction includes a phosphor slab that has a first index of refraction for converting at least a portion of light at a first wavelength to light at a longer second wavelength; and a structured layer that is disposed on the phosphor slab and has a second index of refraction that is smaller than the first index of refraction. The structured layer includes a plurality of structures that are disposed directly on the phosphor slab and a plurality of openings that expose the phosphor slab. The light converting construction further includes a structured overcoat that is disposed directly on at least a portion of the structured layer and a portion of the phosphor slab in the plurality of openings. The structured overcoat has a third index of refraction that is greater than the second index of refraction.

Abstract: Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a first semiconductor layer for absorbing at least a portion of light at a first wavelength; a semiconductor potential well for converting at least a portion of the light absorbed at the first wavelength to light at a longer second wavelength; and a second semiconductor layer that is capable of absorbing at least a portion of light at the first wavelength. The first semiconductor layer has a maximum first index of refraction at the second wavelength. The second semiconductor layer has a second index of refraction at the second wavelength that is greater than the maximum first index of refraction.

Abstract: Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a semiconductor potential well for converting at least a portion of light at a first wavelength to light at a longer second wavelength; an outer layer that is disposed on the semiconductor potential well and has a first index of refraction; and a structured layer that is disposed on the outer layer and has a second index of refraction that is smaller than the first index of refraction. The structured layer includes a plurality of structures that are disposed directly on the outer layer and a plurality of openings that expose the outer layer. The semiconductor light converting construction further includes a structured overcoat that is disposed directly on at least a portion of the structured layer and a portion of the outer layer in the plurality of openings. The overcoat has a third index of refraction that is greater than the second index of refraction.

Abstract: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.

Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: A hybrid torsion beam axle assembly is provided, which includes a steel torsion beam. An end cap is fastened to an end portion of the steel torsion beam, and a cast trailing arm is cast about the end portion of the steel torsion beam including the end cap. In this way, the cast trailing arm is positively and rigidly secured to the steel torsion beam.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

Abstract: Methods and compositions are provided that include a water-in-oil composition comprising an oil-based continuous phase and a discontinuous phase that comprises at least a plurality of hydrogel droplets and a method comprising providing a water-in-oil emulsion comprising an oil-based continuous phase and a discontinuous phase that comprises at least a plurality of hydrogel droplets; and placing the water-in-oil emulsion in a well bore penetrating a subterranean formation. Additional methods are also provided.

Abstract: A silicone mold comprising and oxidized, patterned surface and a layer of perfluoroether silane release agent is described. The mold enables 2nd generation silicone molds to be replicated, i.e. silicone molds from silicone molds.