Quantum dot devices with gate interface materials
Disclosed herein are quantum dot devices with gate interface materials, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.
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This application is a national stage application under 35 U.S.C. § 371 of PCT International Application Serial No. PCT/US2016/036829, filed on Jun. 10, 2016 and entitled “QUANTUM DOT DEVICES WITH GATE INTERFACE MATERIALS,” which is hereby incorporated herein by reference in its entirety.
BACKGROUNDQuantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
Disclosed herein are quantum dot devices with cap layers, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.
The quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits (“qubits”) in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. As used herein, a “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide.
The quantum dot device 100 may include a base 102 and multiple fins 104 extending away from the base 102. The base 102 and the fins 104 may include a substrate and a quantum well stack (not shown in
Although only two fins, 104-1 and 104-2, are shown in
As noted above, each of the fins 104 may include a quantum well layer (not shown in
The fins 104 may be arranged in parallel, as illustrated in
Multiple gates may be disposed on each of the fins 104. In the embodiment illustrated in
As shown in
In some embodiments, the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 104 and the corresponding gate metal). The gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114.
The gate interface material 167 may provide an interface between the quantum well stack (discussed below with reference to the quantum well stacks 146) and the gate dielectric 114, and in particular, the gate interface material 167 may provide an interface between the quantum well stack and the gate dielectric 114 that has a low total interface trap density (Dit), reducing the likelihood of scattering that may impede the coherence of the quantum dots 142 formed in the quantum dot device 100. The inclusion of the gate interface material 167 may thus improve performance relative to embodiments in which the gate interface material 167 is not included.
The gate interface material 167 may include any suitable material to improve the Dit of the gates 106/108 on the quantum well stack. In some embodiments, the gate interface material 167 may include silicon. Silicon may be a particularly useful material for the gate interface material 167 when the quantum well stack includes silicon germanium, and the gate interface material 167 is disposed on the silicon germanium. In some embodiments in which the gate interface material 167 includes silicon, the silicon may oxidize (e.g., due to air exposure before the gate dielectric 114 is formed) to form a layer of silicon oxide at the interface between the silicon of the gate interface material 167 and the gate dielectric 114. In some embodiments, the gate interface material 167 may include aluminum nitride, aluminum oxynitride, or germanium oxide. In embodiments in which the gate interface material 167 includes germanium oxide, the gate interface material 167 may be formed by forming a layer of germanium, then allowing the layer of germanium to oxidize.
In some embodiments, the gate interface material 167 may be a thin layer grown by epitaxy on a quantum well stack. For example, in embodiments in which the quantum well stack includes a silicon germanium barrier between a quantum well layer and the gate 106/108 (e.g., as discussed below with reference to
Each of the gates 106 may include a gate metal 110 and a hardmask 116. The hardmask 116 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 110 may be disposed between the hardmask 116 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 110 and the fin 104. Only one portion of the hardmask 116 is labeled in
Each of the gates 108 may include a gate metal 112 and a hardmask 118. The hardmask 118 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 112 may be disposed between the hardmask 118 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 112 and the fin 104. In the embodiment illustrated in
The gate 108-1 may extend between the proximate spacers 134 on the sides of the gate 106-1 and the gate 106-2, as shown in
The dimensions of the gates 106/108 may take any suitable values. For example, in some embodiments, the z-height 166 of the gate metal 110 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 112 may be in the same range. In embodiments like the ones illustrated in
As shown in
The fins 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100. For example, an n-type doped region 140 may supply electrons for electron-type quantum dots 142, and a p-type doped region 140 may supply holes for hole-type quantum dots 142. In some embodiments, a doped region interface material 141 may be disposed at a surface of a doped region 140, as shown. The doped region interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140. The doped region interface material 141 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region 140 includes silicon, the doped region interface material 141 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference to
The quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots 142. Note that the polarity of the voltages applied to the gates 106/108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100. In embodiments in which the charge carriers are electrons (and thus the quantum dots 142 are electron-type quantum dots), amply negative voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply positive voltages applied to a gate 106/108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which an electron-type quantum dot 142 may form). In embodiments in which the charge carriers are holes (and thus the quantum dots 142 are hole-type quantum dots), amply positive voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply negative voltages applied to a gate 106 and 108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which a hole-type quantum dot 142 may form). The quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots.
Voltages may be applied to each of the gates 106 and 108 separately to adjust the potential energy in the quantum well layer under the gates 106 and 108, and thereby control the formation of quantum dots 142 under each of the gates 106 and 108. Additionally, the relative potential energy profiles under different ones of the gates 106 and 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots 142 under adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142 under a gate 106 and another quantum dot 142 under a gate 108) are separated by only a short potential barrier, the two quantum dots 142 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 106/108 may be adjusted by adjusting the voltages on the respective gates 106/108, the differences in potential between adjacent gates 106/108 may be adjusted, and thus the interaction tuned.
In some applications, the gates 108 may be used as plunger gates to enable the formation of quantum dots 142 under the gates 108, while the gates 106 may be used as barrier gates to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108. In other applications, the gates 108 may be used as barrier gates, while the gates 106 are used as plunger gates. In other applications, quantum dots 142 may be formed under all of the gates 106 and 108, or under any desired subset of the gates 106 and 108.
Conductive vias and lines may make contact with the gates 106/108, and to the doped regions 140, to enable electrical connection to the gates 106/108 and the doped regions 140 to be made in desired locations. As shown in
During operation, a bias voltage may be applied to the doped regions 140 (e.g., via the conductive vias 136 and the doped region interface material 141) to cause current to flow through the doped regions 140. When the doped regions 140 are doped with an n-type material, this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).
The conductive vias 120, 122, and 136 may be electrically isolated from each other by an insulating material 130. The insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. As known in the art of integrated circuit manufacturing, conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias 120/122/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments, conductive lines (not shown) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of conductive vias shown in
As discussed above, the structure of the fin 104-1 may be the same as the structure of the fin 104-2; similarly, the construction of gates 106/108 on the fin 104-1 may be the same as the construction of gates 106/108 on the fin 104-2. The gates 106/108 on the fin 104-1 may be mirrored by corresponding gates 106/108 on the parallel fin 104-2, and the insulating material 130 may separate the gates 106/108 on the different fins 104-1 and 104-2. In particular, quantum dots 142 formed in the fin 104-1 (under the gates 106/108) may have counterpart quantum dots 142 in the fin 104-2 (under the corresponding gates 106/108). In some embodiments, the quantum dots 142 in the fin 104-1 may be used as “active” quantum dots in the sense that these quantum dots 142 act as qubits and are controlled (e.g., by voltages applied to the gates 106/108 of the fin 104-1) to perform quantum computations. The quantum dots 142 in the fin 104-2 may be used as “read” quantum dots in the sense that these quantum dots 142 may sense the quantum state of the quantum dots 142 in the fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in the fin 104-1, and may convert the quantum state of the quantum dots 142 in the fin 104-1 into electrical signals that may be detected by the gates 106/108 on the fin 104-2. Each quantum dot 142 in the fin 104-1 may be read by its corresponding quantum dot 142 in the fin 104-2. Thus, the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation.
The quantum dot devices 100 disclosed herein may be manufactured using any suitable techniques.
The outer spacers 134 on the outer gates 106 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140 into the area under the gates 106/108. As shown, the doped regions 140 may extend under the adjacent outer spacers 134. In some embodiments, the doped regions 140 may extend past the outer spacers 134 and under the gate metal 110 of the outer gates 106, may extend only to the boundary between the outer spacers 134 and the adjacent gate metal 110, or may terminate under the outer spacers 134 and not reach the boundary between the outer spacers 134 and the adjacent gate metal 110. Examples of such embodiments are discussed below with reference to
As discussed above, the base 102 and the fin 104 of a quantum dot device 100 may be formed from a substrate 144 and a quantum well stack 146 disposed on the substrate 144. The quantum well stack 146 may include a quantum well layer in which a 2DEG may form during operation of the quantum dot device 100. The gate interface material 167 may be formed on the quantum well stack 146, and may act as an interface between the quantum well stack 146 and the gate dielectric 114. The quantum well stack 146 may take any of a number of forms, several of which are illustrated in
As discussed above with reference to
In some embodiments, the quantum well layer 152 of
The substrate 144 and the quantum well stack 146 may be distributed between the base 102 and the fins 104 of the quantum dot device 100, as discussed above. This distribution may occur in any of a number of ways. For example,
In the base/fin arrangement 158 of
In the base/fin arrangement 158 of
In the base/fin arrangement 158 of
Although the fins 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins 104 may have any suitable shape (e.g., shape appropriate to the manufacturing processes used to form the fins 104). For example, as illustrated in the base/fin arrangement 158 of
In the embodiment of the quantum dot device 100 illustrated in
As noted above, a single fin 104 may include multiple groups of gates 106/108, spaced apart along the fin by a doped region 140.
As discussed above with reference to
As discussed above with reference to
As discussed above with reference to
In some embodiments, the gate stack formed on the fin 104 (e.g., as discussed above with reference to the gate stack 174 of
In some embodiments, both the gates 106 and the gates 108 may be first formed of dummy materials, then later replaced by real materials.
As noted above, any suitable techniques may be used to manufacture the quantum dot devices 100 disclosed herein.
At 1002, a gate interface material may be provided on a quantum well stack. For example, a gate interface material 167 may be provided on a quantum well stack 146 (e.g., as discussed above with reference to
At 1004, a gate dielectric may be provided on the gate interface material. For example, a gate dielectric 114 may be provided on a gate interface material 167 (e.g., as discussed above with reference to
At 1006, a gate metal may be provided such that the gate dielectric is disposed between the gate interface material and the gate metal. For example, a gate metal 110 or 112 may be provided such that the gate dielectric 114 is disposed between the gate interface material 167 and the gate metal 110 or 112 (e.g., as discussed above with reference to
A number of techniques are disclosed herein for operating a quantum dot device 100.
Turning to the method 1020 of
At 1024, one or more voltages may be applied to one or more gates on a second quantum well stack region to cause a second quantum dot to form in the second quantum well stack region. For example, one or more voltages may be applied to the gates 106/108 on a fin 104-2 (extending away from the base 102 and spaced apart from the fin 104-1 by the insulating material 128) to cause at least one quantum dot 142 to form in the fin 104-2.
At 1026, a quantum state of the first quantum dot may be sensed with the second quantum dot. For example, a quantum dot 142 in the fin 104-2 (the “read” fin) may sense the quantum state of a quantum dot 142 in the fin 104-1 (the “active” fin).
Turning to the method 1040 of
At 1044, a voltage may be applied to a second gate disposed on the quantum well stack region to cause a second quantum dot to form in a second quantum well in the quantum well stack region under the second gate. For example, a voltage may be applied to the gate 108-2 disposed on the fin 104 to cause a second quantum dot 142 to form in the quantum well layer 152 in the fin 104 under the gate 108-2.
At 1046, a voltage may be applied to a third gate disposed on the quantum well stack region to (1) cause a third quantum dot to form in a third quantum well in the quantum well stack region under the third gate or (2) provide a potential barrier between the first quantum well and the second quantum well. At least one gate on the quantum well stack region may include a gate dielectric and a gate interface material disposed between the gate dielectric in the first quantum well stack region (e.g., the gate dielectric 114 and the gate interface material 167). For example, a voltage may be applied to the gate 106-2 to (1) cause a third quantum dot 142 to form in the quantum well layer 152 in the fin 104 (e.g., when the gate 106-2 acts as a “plunger” gate) or (2) provide a potential barrier between the first quantum well (under the gate 108-1) and the second quantum well (under the gate 108-2) (e.g., when the gate 106-2 acts as a “barrier” gate).
The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum dot devices 100 disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices 100, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot). The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 1402.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.
The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
The following paragraphs provide examples of various ones of the embodiments disclosed herein.
Example 1 is a quantum dot device, including: a quantum well stack; a gate interface material; and a high-k gate dielectric; wherein the gate interface material is disposed between the high-k gate dielectric and the quantum well stack.
Example 2 may include the subject matter of Example 1, and may further specify that the gate interface material includes silicon.
Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the quantum well stack includes a barrier layer and a quantum well layer, the barrier layer is disposed between the quantum well layer and the gate interface material, and the gate interface material is disposed on the barrier layer.
Example 4 may include the subject matter of Example 3, and may further specify that the barrier layer is formed of silicon germanium.
Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the quantum well stack includes a quantum well layer formed of silicon.
Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the gate interface material includes silicon oxide.
Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the gate interface material has a thickness between 1 nanometers and 3 nanometers.
Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the gate interface material has a U-shape cross-section.
Example 9 may include the subject matter of any of Examples 1-8, and may further include: a gate metal; and first and second spacers; wherein the gate metal is disposed between the first and second spacers, and the high-k gate dielectric is disposed between the gate metal and the gate interface material.
Example 10 may include the subject matter of Example 9, and may further specify that the gate interface material extends up sides of the first and second spacers such that the gate interface material is disposed between the gate metal and the first and second spacers.
Example 11 may include the subject matter of any of Examples 1-10, and may further specify that the quantum well stack is included in a fin extending from a base.
Example 12 may include the subject matter of Example 11, and may further specify that the quantum well stack is a first quantum well stack, the fin is a first fin, and the quantum dot device further includes: a second fin, including a quantum well stack, extending from the base; and an insulating material disposed between the first and second fins.
Example 13 is a method of operating a quantum dot device, including: applying one or more voltages to gates on a first quantum well stack region to cause a first quantum dot to form in the first quantum well stack region, wherein at least one gate on the first quantum well stack region includes a gate metal and a gate dielectric, and wherein a gate interface material is disposed between the gate dielectric and the first quantum well stack region; applying one or more voltages to gates on a second quantum well stack region to cause a second quantum dot to form in the second quantum well stack region; and sensing a quantum state of the first quantum dot with the second quantum dot.
Example 14 may include the subject matter of Example 13, and may further specify that applying the one or more voltages to the gates on the first quantum well stack region comprises applying a voltage to a first gate to cause the first quantum dot to form in the first quantum well stack region under the first gate.
Example 15 may include the subject matter of any of Examples 13-14, and may further include: applying the one or more voltages to the gates on the first quantum well stack region to cause a third quantum dot to form in the first quantum well stack region; and prior to sensing the quantum state of the first quantum dot with the second quantum dot, allowing the first and third quantum dots to interact.
Example 16 may include the subject matter of any of Examples 13-15, and may further specify that silicon oxide is disposed between the gate interface material and the gate dielectric.
Example 17 is a method of manufacturing a quantum dot device, including: providing a gate interface material on a quantum well stack; providing a gate dielectric on the gate interface material; and providing a gate metal on the gate dielectric such that the gate dielectric is disposed between the gate interface material and the gate metal.
Example 18 may include the subject matter of Example 17, and may further specify that providing the gate interface material on the quantum well stack includes growing the gate interface material by epitaxy.
Example 19 may include the subject matter of any of Examples 17-18, and may further specify that the gate interface material includes silicon, the quantum well stack includes a silicon germanium barrier layer, the gate interface material is provided on the silicon germanium barrier layer, and the silicon germanium barrier layer is disposed between the gate interface material and a quantum well layer of the quantum well stack.
Example 20 may include the subject matter of Example 19, and may further specify that the gate dielectric includes hafnium oxide.
Example 21 may include the subject matter of any of Examples 17-20, and may further include, prior to providing the gate dielectric, exposing the gate interface material to oxygen to form silicon oxide.
Example 22 may include the subject matter of any of Examples 17-21, and may further include, prior to providing the gate interface material: providing a dummy gate stack on the quantum well stack, patterning the dummy gate stack to form a plurality of dummy gate stacks; wherein providing the gate interface material, providing the gate dielectric, and providing the gate metal include replacing the dummy gate stacks with the gate interface material, the gate dielectric and the gate metal, respectively.
Example 23 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes gates on a first quantum well stack region in parallel with gates on a second quantum well stack region, an active quantum well layer in the first quantum well stack region, and a read quantum well layer in the second quantum well stack region, wherein the gates on the first quantum well stack region include a gate dielectric, a gate metal, and a gate interface material disposed between the gate dielectric and the first quantum well stack region; a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to gates on the first and second quantum well stack regions; and a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.
Example 24 may include the subject matter of Example 23, and may further include a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
Example 25 may include the subject matter of any of Examples 23-24, and may further specify that silicon oxide is disposed between the gate interface material and the gate dielectric.
Claims
1. A quantum dot device, comprising:
- a first quantum well stack region, wherein the first quantum well stack region includes an active quantum well layer;
- a first set of gates on the first quantum well stack region, wherein an individual gate in the first set of gates includes a gate interface material, a gate electrode, and a high-k gate dielectric, and the gate interface material is between the high-k gate dielectric and the first quantum well stack region;
- a second quantum well stack region, wherein the second quantum well stack region includes a read quantum well layer; and
- a second set of gates, parallel to the first set of gates, on the second quantum well stack region.
2. The quantum dot device of claim 1, wherein the gate interface material includes silicon.
3. The quantum dot device of claim 1, wherein the first quantum well stack region includes a barrier layer, the barrier layer is between the active quantum well layer and the gate interface material, and the gate interface material is on the barrier layer.
4. The quantum dot device of claim 3, wherein the barrier layer includes silicon germanium.
5. The quantum dot device of claim 1, wherein the active quantum well layer includes silicon.
6. The quantum dot device of claim 1, wherein the gate interface material includes silicon oxide.
7. The quantum dot device of claim 1, wherein the gate interface material has a thickness between 1 nanometers and 3 nanometers.
8. The quantum dot device of claim 1, wherein the gate interface material has a U-shaped cross-section.
9. The quantum dot device of claim 1, further comprising:
- first and second spacers;
- wherein the gate electrode of an individual gate in the first set of gates is between the first and second spacers, and the high-k gate dielectric is between the gate electrode and the gate interface material.
10. The quantum dot device of claim 9, wherein the gate interface material extends up sides of the first and second spacers such that the gate interface material is between the gate electrode and the first and second spacers.
11. The quantum dot device of claim 1, wherein the first quantum well stack region is included in a fin extending from a base.
12. The quantum dot device of claim 11, wherein the fin is a first fin, and the quantum dot device further comprises:
- a second fin, including the second quantum well stack region, extending from the base; and
- an insulating material between the first and second fins.
13. A quantum computing device, comprising:
- a quantum processing device, wherein the quantum processing device includes gates on a first quantum well stack region in parallel with gates on a second quantum well stack region, an active quantum well layer in the first quantum well stack region, and a read quantum well layer in the second quantum well stack region, wherein the gates on the first quantum well stack region include a gate dielectric, a gate metal, and a gate interface material between the gate dielectric and the first quantum well stack region;
- a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to gates on the first and second quantum well stack regions; and
- a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.
14. The quantum computing device of claim 13, further comprising:
- a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
15. The quantum computing device of claim 13, wherein silicon oxide is between the gate interface material and the gate dielectric.
16. The quantum computing device of claim 13, wherein the active quantum well layer includes silicon.
17. The quantum computing device of claim 13, wherein the quantum processing device further includes a barrier layer between the active quantum well layer and the gate interface material, and the barrier layer includes silicon germanium.
18. The quantum computing device of claim 13, wherein the gate interface material has a thickness between 1 nanometers and 3 nanometers.
19. The quantum computing device of claim 13, wherein the gate interface material has a U-shaped cross-section.
20. The quantum computing device of claim 13, wherein the quantum processing device further includes first and second spacers, wherein the gate metal is between the first and second spacers, and the gate dielectric is between the gate metal and the gate interface material.
21. The quantum computing device of claim 20, wherein the gate interface material extends up sides of the first and second spacers such that the gate interface material is between the gate metal and the first and second spacers.
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Type: Grant
Filed: Jun 10, 2016
Date of Patent: Apr 27, 2021
Patent Publication Number: 20190341459
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Ravi Pillarisetty (Portland, OR), Van H. Le (Beaverton, OR), Jeanette M. Roberts (North Plains, OR), David J. Michalak (Portland, OR), James S. Clarke (Portland, OR), Zachary R. Yoscovits (Beaverton, OR)
Primary Examiner: Ali Naraghi
Application Number: 16/306,475
International Classification: H01L 39/22 (20060101); H01L 29/15 (20060101); G06N 10/00 (20190101); H01L 29/165 (20060101); H01L 29/66 (20060101); H01L 29/778 (20060101); H01L 29/78 (20060101); B82Y 10/00 (20110101);