Abstract: A semiconductor device with improved reliability and a method for fabricating the same are provided. The semiconductor device includes a substrate, a first spacer defining a gate trench on the substrate, and a gate electrode in the gate trench, wherein a height of an upper surface of the gate electrode adjacent to the first spacer increases in a direction away from the first spacer.

Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: Embodiments of methods for patterning using enhancement of surface adhesion are presented. In an embodiment, a method for patterning using enhancement of surface adhesion may include providing an input substrate with an anti-reflective coating layer and an underlying layer. Such a method may also include performing a surface adhesion modification process on the substrate, the surface adhesion modification process utilizing a plasma treatment configured to increase an adhesion property of an anti-reflective coating layer without affecting downstream processes. In an embodiment, the method may also include performing a photoresist coating process, a mask exposure process, and a developing process to generate a target patterned structure in a photoresist layer on the substrate. In such embodiments, the method may include controlling operating parameters of the surface adhesion modification process to achieve target profiles of the patterned structure and substrate throughput objectives.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: In a method for processing a target object, the target object includes a wiring layer having a wiring, a diffusion barrier film provided on the wiring layer, an insulating film provided on the diffusion barrier film, and a metal mask provided on the insulating film and having an opening, and the insulating film has a trench formed at a part of a portion exposed through the opening and a first via hole provided at a part of the trench. The method includes: a first step of forming a sacrificial film on the trench and a side surface of the first via hole of the target object; and a second step of forming a second via hole at a deeper portion than a bottom surface of the first via hole by etching the sacrificial film and the insulating film and removing the sacrificial film from the trench and the first via hole.

Abstract: The present disclosure discloses a manufacturing method of an array substrate, an array substrate, a display panel and a display device. The manufacturing method comprises: forming a shielding layer on a base substrate, wherein the shielding layer absorbs light and is made of photoresist; and forming a transistor device layer on the base substrate on which the shielding layer is formed, wherein an orthographic projection of a conductor in the transistor device layer on the base substrate is within an orthographic projection of the shielding layer on the base substrate. The shielding layer can prevent external light from irradiating the conductor in the transistor device layer, and can absorb external light. In addition, the manufacturing process is simple.

Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

Abstract: A method for using a hydrofluorocarbon etching compound selected from the group consisting of 2,2,2-Trifluoroethanamine (C2H4F3N), 1,1,2-Trifluoroethan-1-amine (Iso-C2H4F3N), 2,2,3,3,3-Pentafluoropropylamine (C3H4F5N), 1,1,1,3,3-Pentafluoro-2-Propanamine (Iso-C3H4F5N), 1,1,1,3,3-Pentafluoro-(2R)-2-Propanamine (Iso-2R—C3H4F5N) and 1,1,1,3,3-Pentafluoro-(2S)-2-Propanamine (Iso-2S—C3H4F5N), 1,1,1,3,3,3-Hexafluoroisopropylamine (C3H3F6N) and 1,1,2,3,3,3-Hexafluoro-1-Propanamine (Iso-C3H3F6N) to selectively plasma etching silicon containing films, such as a dielectric antireflective coat (DARC) layer (e.g., SiON), alternating SiO/SiN layers, alternating SiO/p-Si layers, versus a photoresist layer and/or a hard mask layer (e.g., amorphous carbon layer), wherein the photoresist layer is reinforced and SiO/SiN and/or SiO/p-Si are etched non-selectively.

Abstract: An antireflection film is provided on a substrate. The antireflection film includes at least nine layers. An outermost layer of the nine layers is formed by SiO2 or MgF2.

Abstract: Methods and scatterometry overlay metrology tools are provided, which scan a wafer region, perform focus measurements during the scanning to extract therefrom phase information, and derive depth data of the scanned wafer region from the extracted phase information. The depth information, relating to a dimension perpendicular to the wafer, may be derived along lines or surfaces, providing profilometry and surface data, respectively. The depth data may be used to locate metrology targets, as well as to provide material properties concerning wafer layers, to estimate process variation and to improve the overlay measurements.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

Abstract: This invention pertains to UV-absorbing coatings that may optionally be covered with an anti-reflective layer and that are applied to exterior-facing surfaces such as a window or other glass surface that are transparent or translucent. Such coatings are visible to various species of birds, but are generally transparent to humans. The UV absorbing coatings have a silane- or silane-derived chromophore or a combination of a silane- or siloxane-based material and a chromophore, which chromophores absorb UV light at about 300 to about 400 nm. More particularly, the silane- or siloxane-based chromophore is 2-hydroxy-4-(3-triethoxysilylpropoxy) diphenylketone or a derivative thereof.

Abstract: A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (CVD) apparatus to form a contact etch stop layer (CESL) to cover the transistor and the substrate. A temperature of the showerhead is controlled in a range of about 70° C. to about 100° C. to control a temperature of the precursor gases.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: A solar cell is provided, including a substrate, a doped emitter layer, a composite anti-reflective layer, a first electrode, a second electrode, a third electrode and a rear electric field layer, the substrate has a first surface and a second surface opposite to the first surface, the first surface is a light incident surface, the doped emitter layer includes a plurality of convexities disposed on the first surface, the composite anti-reflective layer is formed by combination of a plurality of membranous layers and disposed on the doped emitter layer, the first electrode is disposed on a side of the first surface, the second electrode and the third electrode are disposed on a side of the second surface, the second electrode is a bus electrode, the third electrode is a rear electrode, the rear electric field layer is disposed on the second surface and coupled electrically with the third electrode.

Abstract: An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate.

Abstract: Provided is a method of manufacturing an electronic device, including: forming a first electrode over a substrate forming a first insulating layer over the first electrode; forming a second electrode over the first insulating layer; forming a second insulating layer over the second electrode; and polishing a surface of the second insulating layer by CMP, in which an end portion of the second electrode that is closest to a rim of the substrate is formed at a location closer to the rim of the substrate than an end portion of the first electrode that is closest to the rim of the substrate is.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The process gas includes a first gaseous molecular constituent composed of C, F and optionally H, a second gaseous molecular constituent composed of C, F, and optionally H, and a third gaseous molecular constituent containing atomic hydrogen, diatomic hydrogen, or a CxHy-containing gas, wherein x and y are real numbers greater than zero.

Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, and a selective transmission-reflection layer disposed on the light-emitting structure and including a plurality of dielectric layers having different optical thicknesses alternately stacked at least once. The sum of an optical thickness of a dielectric layer having a maximum optical thickness and an optical thickness of a dielectric layer having a minimum optical thickness is in the range of 0.75 to 0.80.

Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The process gas includes a first gaseous molecular constituent composed of C, F and optionally H, a second gaseous molecular constituent composed of C, F, and optionally H, and a third gaseous molecular constituent composed of C and an element selected from the group consisting of H and F.

Abstract: The present disclosure relates to an integrated chip having a titanium nitride film that provides for a reduced leakage path, and an associated method of formation. In some embodiments, the integrated chip comprises a semiconductor substrate. A titanium nitride film is disposed over the semiconductor substrate. The titanium nitride film comprises a plurality of titanium nitride layers having grain boundaries abutting vertical column-like structures of titanium nitride. The grain boundaries are discontinuous between a top surface of the titanium nitride film and a bottom surface of the titanium nitride film. The discontinuity of the grain boundaries between the different titanium nitride layers reduces leakage paths through the titanium nitride film (e.g., and thereby can improve operation of a MIM capacitor having titanium nitride electrodes).

Abstract: This invention pertains to UV-absorbing coatings that may optionally be covered with an anti-reflective layer and that are applied to exterior-facing surfaces such as a window or other glass surface that are transparent or translucent. Such coatings are visible to various species of birds, but are generally transparent to humans. The UV absorbing coatings have a silane- or silane-derived chromophore or a combination of a silane- or siloxane-based material and a chromophore, which chromophores absorb UV light at about 300 to about 400 nm. More particularly, the silane- or siloxane-based chromophore is 2-hydroxy-4-(3-triethoxysilylpropoxy)diphenylketone or a derivative thereof.

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

Abstract: A method of forming an oxygen-containing ceramic hard mask film on a semiconductor substrate involves receiving a semiconductor substrate in a plasma-enhanced chemical vapor deposition (PECVD) process chamber and depositing forming by PEVCD on the substrate an oxygen-containing ceramic hard mask film, the film being etch selective to low-k dielectric and copper, resistant to plasma dry-etch and removable by wet-etch. The method may further involve removing the oxygen-containing ceramic hard mask film from the substrate with a wet etch. Corresponding films and apparatus are also provided.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.

Abstract: A substrate processing apparatus includes a source gas supply system including a source gas supply pipe connected to a source gas source and a source gas supply controller; a reactive gas supply system including a reactive gas supply pipe connected to a reactive gas source, a reactive gas supply controller, a plasma generation unit and an ion trap unit and an inert gas supply pipe whereat an inert gas supply controller is disposed; a processing chamber supplied with a source gas by the source gas supply system and a reactive gas by the reactive gas supply system; and a control unit configured to control the gas supply controllers. The inert gas supply pipe has a downstream side connected between the reactive gas supply controller and the plasma generation unit and an upstream side connected to an inert gas supply source.

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 ?m metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 ?m metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 ?m metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 ?m thick metal structure having a linewidth/gap of 1.5 ?m/1.5 ?m is finally implemented.

Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.

Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening.

Abstract: A solid-state imaging device includes a photoelectric conversion unit that is formed on a semiconductor substrate, a reading unit that reads signal charges of the photoelectric conversion unit, a gate insulating film and an electrode disposed thereon that constitute the reading unit, a light shielding film that covers the electrode, and an antireflection film that is formed on the photoelectric conversion unit and is constituted by films of four or more layers. The film of the lower layer of the antireflection film is also used as a stopper film during patterning, and a gap between the end of the light shielding film and the semiconductor substrate which is defined by interposing a plurality of films of the lower layer of the antireflection film is set so as to be smaller than the thickness of the gate insulating film.

Abstract: Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.

Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.

Abstract: A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an embodiment, the structures are gate electrodes having a hard mask formed thereon and the spacers are spacers formed alongside the gate electrodes. A photoresist layer is formed over the protective layer, and the photoresist layer may be patterned to remove a portion of the photoresist layer over portions of the protective layer. Thereafter, an etch-back process is performed, such that the protective layer adjacent to the spacers remains to substantially protect the spacers. The hard mask is then removed while the protective layer protects the spacers.

Abstract: A method of forming a thin film pattern includes: forming a thin film on a substrate; forming an amorphous carbon layer including first and second carbon layers on the thin film, wherein the first carbon layer is formed by one of a spin-on method and a plasma enhanced chemical vapor deposition (PECVD) method and the second carbon layer is formed by a physical vapor deposition (PVD) method; forming a hard mask layer on the amorphous carbon layer; forming a PR pattern on the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the PR pattern as an etch mask; forming an amorphous carbon pattern including first and second carbon patterns by etching the amorphous carbon layer using the hard mask pattern as an etch mask; and forming a thin film pattern by etching the thin film using the amorphous carbon pattern.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: Techniques to improve characteristics of processed semiconductor substrates are described, including cleaning a substrate using a preclean process, the substrate comprising a dielectric region and a conductive region, introducing a hydroquinone to the substrate after cleaning the substrate using the preclean operation, and forming a capping layer over the conductive region of the substrate after introducing the hydroquinone.

Abstract: Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention forms at least one pair of gate electrodes having end portions opposed to each other across a gap.

Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.

Abstract: The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.

Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier.

Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.