ELECTRONIC DEVICE WITH CAPCITIVELY COUPLED FLOATING BURIED LAYER
Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
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The field of the invention generally relates to semiconductor devices and methods for fabricating semiconductor devices, and more particularly relates to insulated gate field effect transistor (IGFET) devices.
BACKGROUND OF THE INVENTIONInsulated gate field effect transistor (IGFET) devices are widely used in modern electronic applications. Metal-oxide-semiconductor field effect transistor (MOSFET) devices and lateral-(double)-diffused-metal-oxide-semiconductor (LDMOS) devices are well known examples of such IGFET devices. As used herein, the term metal-oxide-semiconductor and the abbreviation MOS are to be interpreted broadly. In particular, it should be understood that they are not limited merely to structures that use “metal” and “oxide”, but may employ any type of conductor, including “metal”, and any type of dielectric, including “oxide”. The term field effect transistor is abbreviated as “FET”. It is known that improved performance of LDMOS devices can be obtained by using reduced surface field (RESURF) structures.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.
The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose.
As used herein, the term “semiconductor” (abbreviated as “SC”) is intended to include any semiconductor whether single crystal, poly-crystalline or amorphous and to include type IV semiconductors, non-type IV semiconductors, compound semiconductors as well as organic and inorganic semiconductors. Further, the terms “substrate” and “semiconductor substrate” are intended to include single crystal structures, polycrystalline structures, amorphous structures, thin film structures, layered structures as for example and not intended to be limiting, semiconductor-on-insulator (SOI) structures, and combinations thereof The term “semiconductor” is abbreviated as “SC.”
For convenience of explanation and not intended to be limiting, semiconductor devices and methods of fabrication are described herein for silicon semiconductors, but persons of skill in the art will understand that other semiconductor materials may also be used. Additionally, various device types and/or doped SC regions may be identified as being of N type or P type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either N or P type and the second type then is either P or N type.
The use of a floating buried layer RESURF structures represented by the electrical schematic diagrams of
Referring to both
It has further been determined that this condition can be avoided by providing a circuit path by which buried layer 72 can be charge pumped, so that its voltage can also rise rapidly in response to fast transient 95, thereby preventing the localized electric field from rising above that necessary to induce avalanche and premature breakdown. This is accomplished by providing shunt capacitance 94, 94′ between the appropriate source or drain terminal (or source or drain region) and buried layer 72. In the N channel device (see also
Rapid rise time pulses can be readily obtained for test purposes using transmission lines. Such transmission line pulse (TLP) tests are well known in the art. It is found that providing shunt capacitance 94, 94′ improves the transient breakdown voltage so that it equals or exceeds the DC breakdown voltage. This is a much desired result and a significant improvement in the art. The desired magnitude of charge pump capacitance 94, 94′ is discussed later.
Capacitance 94-3 is formed by relatively deep dielectric isolation wall 100, which DC isolates sinker region 86 and BL 72 from sinker region 88 and doped region 722. Dielectric isolation wall 100 has lateral thickness 101 and vertical extent 102 between substrate 70 and STI region 84, and functions as the dielectric layer of capacitance 94-3 between the opposed conductors formed, on the left, by sinker 88 and doped region 722 and, on the right, by sinker 86 and BL 72. Silicon dioxide is a non-limiting example of a suitable dielectric material for capacitance 94-3, but other substantially insulating materials may also be used. Means and methods for providing such dielectric isolation walls are well known in the art, and any convenient means that fulfills the desired characteristics described below may be used. In some embodiments, dielectric isolation wall 100 may comprise a sandwich of dielectric material (e.g., silicon oxide) with a polycrystalline SC (e.g., polysilicon) or other conductive inclusion 103 substantially in the center of the dielectric making up isolation wall 100. When centrally located conductive inclusion 103 is floating, its presence does no harm. Lateral thickness 101 of isolation wall 100 is desirably in the range of about 0.5 to 2.0 micrometers, more conveniently in the range of about 1.0 to 2.0 micrometers and preferably about 1.5 micrometers, although larger or smaller values can also be used. Vertical height 102 of isolation wall 100 approximately from substrate region 701 to the top of sinker 86 is desirably in the range of about 3 to 10 micrometers, more conveniently in the range of about 5 to 9 micrometers and preferably about 8 micrometers, although larger or smaller values can also be used.
The effectiveness of charge pumping into BL 72 using capacitance 94-3 depends upon the magnitude of capacitance 94-3. Persons of skill in the art will understand based on the description herein, that capacitance 94-3 may be increased by decreasing thickness (X) 101, increasing vertical height (Y) 102 and/or increasing the plan view perimeters (Z) of isolation wall 100 forming capacitance 94-3. Stated another way, capacitance C94-3=f((Y)*(Z)/(X)), and any or all of these parameters may be adjusted to obtain the desired magnitude of capacitance. The use of capacitance 94-3 means that BL 72 can continue to be floating for DC and slow AC purposes, so that the advantages of a floating RESURF BL are preserved and there is no adverse affect on the DC breakdown voltage (BVdss)DC or series-ON resistance Rdson while the transient breakdown voltage (BVdss)TR is substantially increased. The arrangement of
Sinker region 86 (e.g., N type) extends from beneath STI region 84 through further SC region 74 to make Ohmic contact to buried layer 72. Conventional gate conductor 45 is provided overlying and insulated from surface 71 between source region 42 and drift region 148 and extending somewhat there-over. Conductors are conventionally provided to couple source region 42, drain region 44 and gate 45 to their respective terminals 47, 48 and 49. When source 42, gate 45 and drain 44 are appropriately biased, channel 90′ forms between source 42 and drain 44. Device 69′-3 has: (i) relatively deep lateral dielectric isolation wall 100, in this example, adjacent sinker region 86 and extending from surface 71 (or from STI region 84) through SC region 74 and BL region 72 into underlying portion 701 of substrate 70, (ii) further sinker region 88 is provided extending from surface 71 through region 74 to further (e.g., N type) region 722 to make Ohmic contact thereto, and (iii) (e.g., N+) contact region 89 is provided to further sinker region 88. Contact region 89 is electrically coupled to source terminal 47 (or source region 42). Further sinker region 88 and underlying region 722 may be a single doped region or may be separately formed, ohmically coupled doped regions of the same conductivity type. Either arrangement is useful.
Capacitance 94′-3 is formed by dielectric isolation wall 100, which DC isolates sinker region 86 and BL 72 from sinker region 88 and doped region 722. The discussion of dielectric isolation wall 100 in connection with
Persons of skill in the art will understand based on the description herein, that charge pump capacitance 94′-3 of P channel device 69′-3 of
Further, with respect to the embodiments of
Referring now to manufacturing stage 211 of
Referring now to manufacturing stage 212 of
Referring now to manufacturing stage 213 of
Referring now to manufacturing stage 214 of
Referring now to manufacturing stage 215 of
Referring now to manufacturing stage 217 of
Referring now to manufacturing stage 218 of
Referring now to manufacturing stage 219, mask 618 is removed. Structure 319 results. Conductive contacts are then made to regions 22, 24, 89, and 78 using teachings well known in the art. The interconnections to couple such regions to source, drain and gate terminals and to couple contact 89 of sinker region 88 to drain region 24 or drain terminal 28 are also formed using teachings well known in the art, thereby providing substantially finished device 69-3 of
According to a first embodiment, there is provided an electronic device (69, 69′), comprising, an MOS transistor (63, 65) having current carrying terminals including a source (22, 42) and a drain (24, 44) in a semiconductor containing body (70, 72, 74) having an upper surface (71), a DC isolated buried layer (72) underlying the MOS transistor (63, 65), and a charge pump capacitance (94, 94′) coupled between one of the current carrying terminals (22, 42; 24, 44) and the DC isolated buried layer (72). According to a further embodiment, the MOS transistor (63) is an N channel transistor and the DC isolated buried layer (72) is N type. According to a still further embodiment, the MOS transistor (65) is a P channel transistor and the DC isolated buried layer (72) is N type. According to a yet further embodiment, the charge pump capacitance (94-1, 94′-1) is external to the MOS transistor (63, 65). According to a still yet further embodiment, the charge pump capacitance (94-2, 94′-2) is formed over the upper surface (71). According to a yet still further embodiment, the charge pump capacitance (94-2, 94′-2) is a deposited capacitance. According to another embodiment, the charge pump capacitance (94-3, 94′-3) is formed under the upper surface (71). According to a still another embodiment, the charge pump capacitance (94-3, 94′-3) comprises a dielectric trench isolation wall (100) penetrating substantially from the upper surface (71) through the DC isolated buried layer (72) underlying the MOS transistor (63, 65). According to a yet another embodiment, the dielectric trench isolation wall (100) has a first sinker region (86) on a first side thereof facing toward the MOS transistor (63, 65) and a second sinker region (88) on a second side thereof facing away from the MOS transistor (63, 65), wherein the first sinker region (86) is Ohmically coupled to the DC isolated buried layer (72) and the second sinker region (88) is Ohmically coupled to one of the source (42) and drain (24) of the MOS transistor (63, 65) and the first (86) and second (88) sinker regions are DC isolated from each other by the dielectric trench isolation wall (100). According to a till yet another embodiment, the MOS transistor (63, 65) is an LDMOS transistor (69, 69′).
According to a second embodiment, there is provided an LDMOS transistor (69, 69′), comprising, a buried SC layer region (72), a further SC region (74) overlying the buried layer region (72) and having an upper surface (71), a MOSFET (63, 65) formed in the further SC region (74), wherein the MOSFET (63, 65) comprises, a body region (76, 154) having therein a source region (22, 42) of the MOSFET (63, 65), and a carrier drift region (80, 148) laterally separated from the body region (76, 154) and having therein a drain region (24, 44) of the MOSFET (63, 65), and a charge pump capacitance (94, 94′) coupled between the buried layer region (72) and one of the drain region (24) and the source region (42) of the MOSFET (63, 65). According to a further embodiment, the charge pump capacitance (94-1, 94′-1; 94-2, 94′-2) is formed substantially over the upper surface (71). According to a still further embodiment, the charge pump capacitance (94-1, 94′-1; 94-2, 94′-2) is formed substantially on the upper surface (71). According to a yet further embodiment, the charge pump capacitance (94-3, 94′-3) is formed substantially beneath the upper surface (71). According to a still yet further embodiment, the charge pump capacitance (94, 94′) has a capacitance value adapted to pump charge into the buried layer (72) in response to a fast voltage transient voltage (95) applied between the source (22, 42) and drain (24, 44) so as to temporarily raise a voltage of the buried layer (72) by at least 5% of the magnitude of fast voltage transient voltage (95). According to a yet still further embodiment, the charge pump capacitance (94, 94′) has a capacitance value adapted to pump charge into the buried layer (72) in response to a fast voltage transient (95) applied between the source (22, 42) and drain (24, 44) so as to temporarily raise the voltage of the buried layer (72) by at least 10% of the magnitude of fast voltage transient voltage (95).
According to a third embodiment, there is provided a method for providing an LDMOS transistor (69, 69′), comprising, forming a buried layer (72) of a first conductivity type, forming a further SC region (74) of a second, opposite, conductivity type on the buried layer (72), and having an upper surface (71), forming a first doped region (80, 154) of the first conductivity type in a first portion of the further SC region (74) extending at least in part to the upper surface (71) and overlying at least part of the buried layer (72), forming a dielectric trench isolation wall (100) extending though the further SC region (74) and the buried layer (72), and laterally separated from the first doped region (80, 154), forming another doped region (76, 148) of the second conductivity type extending into the further semiconductor region (74) between the first doped region (80, 154) and the dielectric trench isolation wall (100) and laterally separated from the first doped region (80, 154) by a portion of the further semiconductor region (74), forming first (86) and second (88) sinker regions of the first conductivity type extending substantially from the surface (71) through the further semiconductor region (74) to make Ohmic contact to the buried layer (72), the first sinker region (86) located on a first side of the dielectric trench isolation wall (100) toward the first doped region (80, 154) and the second sinker region (88) located on a second side of the dielectric trench isolation wall (100) facing away from the first doped region (80, 154) so that, (i) the first (86) and second (88) sinker regions and (ii) portions (722, 723) of the buried layer (72) lying on either side of the dielectric trench isolation wall (100) are DC isolated from each other, providing a second sinker Ohmic contact region (89) of the first conductivity type in the second sinker region (88), wherein if the LDMOS transistor (69, 69′) is an N channel LDMOS transistor (69), providing a drain region (24) of the first conductivity type in the first doped region (80) and Ohmically connecting the second sinker contact region (89) to the drain region (24), and wherein if the LDMOS transistor (69, 69′) is a P channel LDMOS transistor (69′), providing a source region (42) of the second conductivity type in the first doped region (154) and Ohmically connecting the second sinker contact region (89) to the source region (42). According to a further embodiment, the method further comprises, forming a gate insulator with an overlying gate conductor (25, 45) on the upper surface (71) above at least the portion of the further semiconductor region (74) between the first doped region (80, 154) and the another doped region (76, 148). According to a still further embodiment, the LDMOS transistor (69, 69′) is an N channel LDMOS transistor (69) and the source region (22), the drain region (24) and the second sinker Ohmic contact region (89) are formed substantially at the same time. According to a yet further embodiment, the LDMOS transistor (69, 69′) is a P channel LDMOS transistor (69′), and the second sinker Ohmic contact region (89) and a body contact region (46) to the first doped region (154) are formed at substantially the same time.
While at least one exemplary embodiment and method of fabrication has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.
Claims
1. An electronic device, comprising:
- an MOS transistor having current carrying terminals including a source and a drain in a semiconductor containing body having an upper surface;
- a DC isolated buried layer underlying the MOS transistor; and
- a charge pump capacitance coupled between one of the current carrying terminals and the DC isolated buried layer.
2. The electronic device of claim 1, wherein the MOS transistor is an N channel transistor and the DC isolated buried layer is N type.
3. The electronic device of claim 1, wherein the MOS transistor is a P channel transistor and the DC isolated buried layer is N type.
4. The electronic device of claim 1, wherein the charge pump capacitance is external to the MOS transistor.
5. The electronic device of claim 1, wherein the charge pump capacitance is formed over the upper surface.
6. The electronic device of claim 5, wherein the charge pump capacitance is a deposited capacitance.
7. The electronic device of claim 1, wherein the charge pump capacitance is formed under the upper surface.
8. The electronic device of claim 7, wherein the charge pump capacitance comprises a dielectric trench isolation wall penetrating substantially from the upper surface through the DC isolated buried layer underlying the MOS transistor.
9. The electronic device of claim 8, wherein the dielectric trench isolation wall has a first sinker region on a first side thereof facing toward the MOS transistor and a second sinker region on a second side thereof facing away from the MOS transistor, wherein the first sinker region is Ohmically coupled to the DC isolated buried layer and the second sinker region is Ohmically coupled to one of the source and drain of the MOS transistor and the first and second sinker regions are DC isolated from each other by the dielectric trench isolation wall.
10. The electronic device of claim 9, wherein the MOS transistor is an LDMOS transistor.
11. An LDMOS transistor, comprising:
- a buried SC layer region;
- a further SC region overlying the buried layer region and having an upper surface;
- a MOSFET formed in the further SC region, wherein the MOSFET comprises: a body region having therein a source region of the MOSFET, and a carrier drift region laterally separated from the body region and having therein a drain region of the MOSFET; and
- a charge pump capacitance coupled between the buried layer region and one of the drain region and the source region of the MOSFET.
12. The LDMOS transistor of claim 11, wherein the charge pump capacitance is formed substantially over the upper surface.
13. The LDMOS transistor of claim 11, wherein the charge pump capacitance is formed substantially on the upper surface.
14. The LDMOS transistor of claim 11, wherein the charge pump capacitance is formed substantially beneath the upper surface.
15. The LDMOS transistor of claim 11, wherein the charge pump capacitance has a capacitance value adapted to pump charge into the buried layer in response to a fast voltage transient voltage applied between the source and drain so as to temporarily raise a voltage of the buried layer by at least 5% of the magnitude of fast voltage transient voltage.
16. The LDMOS transistor of claim 14, wherein the charge pump capacitance has a capacitance value adapted to pump charge into the buried layer in response to a fast voltage transient applied between the source and drain so as to temporarily raise the voltage of the buried layer by at least 10% of the magnitude of fast voltage transient voltage.
17. A method for providing an LDMOS transistor, comprising:
- forming a buried layer of a first conductivity type;
- forming a further SC region of a second, opposite, conductivity type on the buried layer, and having an upper surface;
- forming a first doped region of the first conductivity type in a first portion of the further SC region extending at least in part to the upper surface and overlying at least part of the buried layer;
- forming a dielectric trench isolation wall extending though the further SC region and the buried layer, and laterally separated from the first doped region;
- forming another doped region of the second conductivity type extending into the further semiconductor region between the first doped region and the dielectric trench isolation wall and laterally separated from the first doped region by a portion of the further semiconductor region;
- forming first and second sinker regions of the first conductivity type extending substantially from the surface through the further semiconductor region to make Ohmic contact to the buried layer, the first sinker region located on a first side of the dielectric trench isolation wall toward the first doped region and the second sinker region located on a second side of the dielectric trench isolation wall facing away from the first doped region so that, (i) the first and second sinker regions and (ii) portions of the buried layer lying on either side of the dielectric trench isolation wall are DC isolated from each other;
- providing a second sinker Ohmic contact region of the first conductivity type in the second sinker region;
- wherein if the LDMOS transistor is an N channel LDMOS transistor, providing a drain region of the first conductivity type in the first doped region and Ohmically connecting the second sinker contact region to the drain region; and
- wherein if the LDMOS transistor is a P channel LDMOS transistor, providing a source region of the second conductivity type in the first doped region and Ohmically connecting the second sinker contact region to the source region.
18. The method of claim 17, further comprising, forming a gate insulator with an overlying gate conductor on the upper surface above at least the portion of the further semiconductor region between the first doped region and the another doped region.
19. The method of claim 17, wherein the LDMOS transistor is an N channel LDMOS transistor and the source region, the drain region and the second sinker Ohmic contact region are formed substantially at the same time.
20. The method of claim 17, wherein the LDMOS transistor is a P channel LDMOS transistor, and the second sinker Ohmic contact region and a body contact region to the first doped region are formed at substantially the same time.
Type: Application
Filed: Mar 30, 2010
Publication Date: Oct 6, 2011
Patent Grant number: 8338872
Applicant: FREESCALE SEMICONDUCTOR, INC. (Austin, TX)
Inventors: Vishnu K. Khemka (Phoenix, AZ), Tahir A. Khan (Tempe, AZ), Ronghua Zhu (Chandler, AZ), Weixiao Huang (Tempe, AZ), Bernhard H. Grote (Phoenix, AZ)
Application Number: 12/750,166
International Classification: H01L 27/06 (20060101); H01L 21/8234 (20060101);