METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS
A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.
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The following regular U.S. patent applications (including this one) are being filed concurrently, and the entire disclosure of the other applications are incorporated by reference into this application for all purposes:
-
- application Ser. No. ______, filed Aug. 4, 2011, entitled “METHOD AND SYSTEM FOR GAN VERTICAL JFET UTILIZING A REGROWN GATE” (Attorney Docket No. 93444-808244(000600US);
- application Ser. No. ______, filed Aug. 4, 2011, entitled “METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL” (Attorney Docket No. 93444-80824436(000700US)); and
- application Ser. No. ______, filed Aug. 4, 2011, entitled “METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS” (Attorney Docket No. 93444-808239(000900US)).
Power electronics are widely used in a variety of applications. Power electronic devices are commonly used to modify a form of electrical energy, for example, voltage or current converters. Such converters can operate over a wide range of power levels, from milliwatts in mobile devices to hundreds of megawatts in a high voltage power transmission system). Despite the progress made in power electronics, there is a need in the art for improved electronics systems and methods of operating the same.
SUMMARY OF THE INVENTIONThe present invention relates generally to electronic devices. More specifically, the present invention relates to methods and systems for forming p-n junctions in III-V material systems. Merely by way of example, the invention has been applied to methods and systems for displacing a p-n junction from a regrowth interface in a III-nitride based semiconductor device. The methods and techniques can be applied to a variety of compound semiconductor systems including transistors, diodes, and other electronic and optoelectronic devices.
According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.
According to another embodiment of the present invention, a method of forming a lateral p-n junction in III-nitride materials is provided. The method includes providing an n-type III-nitride substrate and forming an n-type epitaxial layer coupled to the n-type III-nitride substrate. The method also includes removing at least a portion of the n-type epitaxial layer to define an n-type structure and diffusing an acceptor into a predetermined portion of the n-type epitaxial structure. The method further includes regrowing a p-type epitaxial layer electrically coupled to the predetermined portion of the n-type epitaxial structure.
According to a specific embodiment of the present invention, a method of fabricating a lateral p-n junction is provided. The method includes providing a III-nitride substrate having a first conductivity type and forming a diffusion mask over a predetermined portion of the III-nitride substrate. The method also includes forming a dopant source including a dopant in contact with at least an exposed portion of the III-nitride substrate and diffusing the dopant into the III-nitride substrate to form a diffusion region having a second conductivity type different from the first conductivity type.
According to another specific embodiment of the present invention, a method of forming a lateral p-n junction is provided. The method includes providing a substrate comprising a GaN-based material characterized by a first conductivity type and forming a masking layer on a surface of the substrate. The method also includes removing a predetermined portion of the substrate using an ex-situ etch process and removing an additional predetermined portion of the substrate using an in-situ etch process. The method further includes regrowing a GaN-based material characterized by a second conductivity type in at least a portion of the predetermined portion and the additional predetermined portion of the substrate.
Numerous benefits are achieved by way of the present invention over conventional techniques. For example, embodiments of the present invention provide improved p-n junction quality with reduced leakage current or other current-voltage (I-V) characteristics in comparison with conventional techniques. Some embodiments provide a p-n junction region characterized by a reduced number of structural defects resulting, for example, from etching damage, chemical contamination, exposure to air, or the like. Embodiments of the present invention provide devices with reduced Shockley-Read-Hall recombination at the junction, thereby reducing leakage current in response to application of a bias voltage. In some implementations, the quality of the p-n junction is comparable to that of a p-n junction formed by a continuous growth process. These and other embodiments of the invention along with many of its advantages and features are described in more detail in conjunction with the text below and attached figures.
Embodiments of the present invention relate to electronic devices. More specifically, the present invention relates to methods and systems for forming p-n junctions in III-V material systems. Merely by way of example, the invention has been applied to methods and systems for displacing a p-n junction from a regrowth interface in a III-nitride based semiconductor device. The methods and techniques can be applied to a variety of compound semiconductor systems including transistors, diodes, and other electronic and optoelectronic devices.
GaN-based electronic and optoelectronic devices are undergoing rapid development. Desirable properties associated with GaN and related alloys and heterostructures include high bandgap energy for visible and ultraviolet light emission, favorable transport properties (e.g., high electron mobility and saturation velocity), a high breakdown field, and high thermal conductivity. Many GaN-based devices include planar p-n junctions, typically formed in a single growth step. However, some classes of GaN-based devices incorporate a lateral p-n junction.
Referring to
As illustrated in
The etch/regrowth mask 102 is removed as illustrated in
The device 100 illustrated in
Referring to
As an example, some chemical contamination of the regrowth surface may result from residual contamination from the etch gases used during the etch process, which is typically a reactive ion etching (RIE) process. Additionally, when the material is removed from the etch chamber, oxidation of the surface or adhesion of one or more impurities on the surface can result in chemical contamination of the regrowth interface.
Additionally, the inventors have determined that structural damage may be present at the regrowth interface due, for example, to the fact that GaN-based materials are quite hard and present issues for the etching processes that are commonly used and typically utilize a significant sputtering component. Thus, both chemical contamination and structural damage can be present at the regrowth interface. Regrowth on this type of surface will typically result in the formation of a p-n junction that is characterized by less than optimal electrical characteristics including leakage currents. Without limiting embodiments of the present invention, the inventors believe that mid-gap states result from the chemical contamination and/or structure damage, thereby contributing, in part, to the leakage currents.
According to embodiments of the present invention described throughout the present specification, the junction I-V characteristics are improved by performing an impurity diffusion before the regrowth process. In this manner, the p-n junction is displaced from the regrowth interface. Consequently, the p-n junction is formed in bulk material and spaced a predetermined distance from surfaces that have been rendered imperfect by, for example, structural damage, chemical contamination, or the like. Thus, embodiments of the present invention provide p-n junctions that have diode I-V characteristics that are improved in comparison with conventional techniques.
Embodiments of the present invention provide methods and systems in which an improved surface characterized by high interface quality is provided for a p-n junction, for example, by moving the p-n junction into bulk material through a diffusion process or, for example, by forming a new surface associated with the p-n junction using an etching process. Additional description of these methods and techniques is provided throughout the specification and more particularly below.
As described more fully throughout the present specification, a diffusion process can be utilized prior to regrowth to shift the location of the p-n junction away from the regrowth interface and into the bulk of the substrate. In some embodiments, zinc, which is a deep acceptor, with activation energy in the range 400-500 meV, will compensate for the n-type doping of the substrate and shift the p-n junction from the etched surface to the pristine bulk material. In some embodiments, lateral p-n junctions are formed by zinc diffusion, which is not obvious for III-nitride systems as a result of the deep acceptor characteristics of zinc diffused in such materials including GaN. Utilizing embodiments of the present invention, there are fewer structural defects from etching processes and/or chemical contamination from etching/air-exposure in the vicinity of the p-n junction. This reduces SRH recombination at the junction, which is responsible for leakage current when bias voltage is applied.
Although the substrate 301 is illustrated as a single material, multiple materials in one or more layers can be included in the term substrate. Additionally, although a GaN substrate is illustrated in
Prior to the selective regrowth process, a diffusion process is performed to diffuse a dopant with a different conductivity type than the substrate into the bulk of the substrate material. Referring to
Embodiments of the present invention utilize one of several techniques to diffuse the donor or acceptor from a variety of sources in one of several manners. The following processes are described for purposes of illustration and are not intended to limit the scope of the present invention. The dopant (e.g., zinc) may be diffused either in-situ or ex-situ from a variety of sources. As an example, the dopant can be provided by a vapor source, such as diethyl- or dimethyl-zinc with ammonia and carrier gases in an MOCVD reactor. Merely by way of example, the device to be diffused could be placed in an open furnace through which the zinc precursor is flowed. As another example, the dopant can be provided by a vapor source in a closed ampoule or boat such as a zinc source that evaporates upon heating to provide a high vapor concentration. The high partial pressure of the dopant would be the driving force for the diffusion process in this example.
As another example, a solid source of the dopant-containing material (e.g., solid zinc or a zinc-containing material such as zinc oxide or the like) could be deposited or otherwise formed on an exposed surface of the device and then used as the dopant source during the diffusion process. In order to prevent evaporation of the dopant-containing source during the diffusion process, the dopant-containing source could be capped with a material having a lower vapor pressure than the dopant-containing material. Examples of materials that could be used as capping materials include dielectric materials such as silicon nitride, silicon oxide, or the like.
The dopant could be zinc itself, or some volatile zinc-containing material such as zinc arsenide, zinc oxide, or the like. In other embodiments, other donors or acceptors can be used during the diffusion process, including, without limitation, compounds including zinc, for instance, diethyl-zinc or dimethyl-zinc discussed above, compounds including magnesium, for example, biscyclopentadienylmagnesium, magnesium-doped SiN, compounds including beryllium, for example diethyl-beryllium or solid beryllium-oxide films, compounds including carbon, for example carbon tetrachloride, carbon tetrabromide, or solid carbon films, combinations thereof, or the like.
Metal electrode regions including one or more metals or metal alloys are formed, using, for example a deposition and patterning process to form the metal electrode contacts 307 to the n-type GaN substrate and the metal electrode contacts 306 to the p-type GaN regrown material. Using the process illustrated in
Referring to
Thus, according to embodiments of the present invention, excessive leakage current associated with the regrown lateral p-n junction is decreased. As illustrated in
A selective dopant diffusion (e.g., a zinc diffusion) (356) is performed in the MOCVD chamber using a proper combination of process parameters including pressure, flow (e.g., ammonia, N2/H2 carriers, dopant precursor such as a diethyl zinc precursor, a dimethyl zinc precursor, a biscyclopentadienylmagnesium precursor, or the like), time, temperature, and the like. In this embodiment, the etch mask also serves as a diffusion mask. A material of a conductivity type opposite to the conductivity type of the III-nitride substrate (e.g., p-type GaN) is selectively grown selectively in the recessed region forming during the etching process (358). The structure is removed from the MOCVD reactor, the mask is removed, and electrodes may be deposited on the p-type and n-type regions (360). An electrode on the p-type region is not present in all embodiments.
Embodiments of the present invention are applicable to a variety of semiconductor devices including electronic/optoelectronic devices including a p-n junction. For example transverse junction (TJ) laser diodes, vertical junction field-effect transistors (VJFETs), and the like.
It should be appreciated that the specific steps illustrated in
Referring to
The dopant (e.g., zinc) may be diffused in-situ or ex-situ from a solid source such as a zinc-containing source deposited on the surface of the substrate. Examples of solid sources include Zn itself, zinc oxide, or the like. Using these embodiments, a lateral p-n junction is formed by selective zinc diffusion using a solid source.
A diffusion process is used to drive the material from the diffuse source into the bulk of the substrate 401 as illustrated by diffusion region 412 in
The inventors have determined that a number of acceptor species are suitable for diffusion in GaN including Mg, C, and Zn. Of these acceptor species, zinc is likely the fastest diffuser and zinc diffusion has been observed for growth of GaN on ZnO substrates and shallow zinc diffusions have been performed for improving ohmic contacts. Based on these observations and the strong visible emission from Si+Zn (donor+acceptor) codoped LEDs, the inventors have determined that zinc is an active deep acceptor, making zinc diffusion a viable process for formation of p-n junctions in III-nitride material systems including GaN-based systems.
In the embodiment illustrated in
It should be appreciated that the specific steps illustrated in
According to other embodiments of the present invention, the junction I-V characteristic may be improved by performing an in-situ etch and clean before regrowth. As described more fully below, the damaged and contaminated region of the device is removed, allowing the subsequent regrowth to be performed on a high quality and clean surface. Consequently the p-n junction formed at this interface will be of higher structural quality and chemical purity. Embodiments of the present invention provide p-n junctions with a diode I-V characteristic that is characterized by reduced leakage in comparison with conventional devices.
The amount of material removed during the in-situ etch process is selected to remove damage caused during the ex-situ etch process so that the depletion region formed by the p-n junction is separated from such damage. The increase in width of the etched cavity during the in-situ etch process will be a function of the particular ex-situ etch processes utilized, with ex-situ etch processes characterized by greater damage penetration values being associated with wider in-situ etch processes.
After the in-situ etch, a material with a conductivity type different from the substrate 501 is regrown, illustrated in
Referring to
The process illustrated in
The in-situ etch may be accomplished in one of several manners such as by H2 etching, by using a corrosive chemical such as HCl or Cl2 gas flowing into the MOCVD chamber. The use of H2 etching is readily implemented since H2 is typically available in the MOCVD reactor. By proper adjustment of the gas variables, including the H2, N2, and/or NH3 flows, pressure, and temperature, the etch rate may be controlled. In an alternative embodiment using regrowth of material by hydride vapor phase epitaxy (VPE), the in-situ etch can be performed with Cl2 or HCl. According to embodiments of the present invention, the in-situ etching exposes a pristine crystal structure/surface, with no opportunity for contamination by air exposure.
Since the structural damage, chemical contamination, combinations thereof, or the like are reduced or eliminated during the in-situ etch step, the p-n junction quality is comparable to that of a near-ideal p-n junction formed by a continuous growth process. In other embodiments, the subsequent regrowth processes are performed on the in-situ etched surfaces, providing a higher material quality than available using ex-situ etched surfaces. Thus, the I-V characteristic of a p-n junction grown using the process illustrated in
After the in-situ etch process, material (e.g., p-type GaN) is selectively regrown in the recessed region (558). The etch/regrowth mask is removed and electrodes can be formed (560), for example, a metal electrode to contact the substrate (e.g., the n-type GaN substrate) and a metal electrode to contact to the regrown region (e.g., the p-type GaN region).
It should be appreciated that the specific steps illustrated in
Embodiments of the present invention provide benefits not available using conventional techniques since the p-n junction can be present in bulk material at a location displaced from growth and/or regrowth interfaces. In some embodiments, a GaN bulk region is provided and a portion of the GaN bulk region is removed, for example, using an etching process to form a remaining portion of the GaN bulk region. In examples using etching, an etch interface is formed at the periphery of the remaining portion of the GaN bulk region. The etch interface is characterized by a first density of structural defects per unit area.
The p-n junction is formed at a location between the etch interface and the GaN bulk region as illustrated by the embodiments described herein. The p-n junction is characterized by a second density of structural defects per unit area less than the first density. Thus, by displacing the p-n junction into the bulk, the quality of material in the vicinity of the p-n junction is improved in comparison with conventional structures, thereby improving electrical device performance. In addition to structural defect densities, the etch interface and the p-n junction can have chemical defect densities associated therewith. According to some embodiments of the present invention, the chemical defect density of the p-n junction is less than the chemical defect density of the etch interface. The higher purity of the material at the p-n junction interface improves electrical performance as well as other device properties. In embodiments in which regrowth processes are utilized, the etch interface can also be a regrowth interface that is spatially separated from the p-n junction by a predetermined distance in contrast with conventional devices in which they would be coincidental.
Referring once again to
Embodiments of the present invention are applicable to devices including vertical junction FETs (JFETs), which can utilize lateral p-n junctions to change the depletion region width across a channel, but embodiments of the present invention are not limited to these device architectures and are also applicable to any structure including lateral p-n junctions, junction barrier Schottky diodes, or devices with regrown channels. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Claims
1. A semiconductor device comprising:
- a III-nitride substrate having a first conductivity type;
- a first electrode electrically coupled to the III-nitride substrate;
- a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface; and
- a p-n junction disposed between the III-nitride substrate and the regrowth interface.
2. The semiconductor device of claim 1 further comprising a second electrode electrically coupled to the III-nitride material having the second conductivity type.
3. The semiconductor device of claim 1 wherein a structural defect concentration associated with the lateral p-n junction is less than a structural defect concentration associated with a region laterally adjacent the lateral p-n junction.
4. The semiconductor device of claim 1 wherein the III-nitride substrate comprises an n-type GaN material.
5. The semiconductor device of claim 1 wherein the III-nitride material having the second conductivity type comprises a p-type GaN material.
6. The semiconductor device of claim 5 wherein the III-nitride material having the second conductivity type comprises an acceptor diffused region disposed between the regrowth interface and the p-n junction.
7. The semiconductor device of claim 6 wherein the acceptor region comprises a diffusion region including at least one of zinc, magnesium, beryllium, or calcium.
8. The semiconductor device of claim 1 wherein the p-n junction extends in a direction substantially orthogonal to a growth direction of the III-nitride material having the second conductivity type.
9. The semiconductor device of claim 1 wherein the III-nitride substrate is characterized by a growth surface substantially coplanar with a surface of the first electrode.
10. A method of forming a lateral p-n junction in III-nitride materials, the method comprising:
- providing an n-type III-nitride substrate;
- forming an n-type epitaxial layer coupled to the n-type III-nitride substrate;
- removing at least a portion of the n-type epitaxial layer to define an n-type structure;
- diffusing an acceptor into a predetermined portion of the n-type epitaxial structure; and
- regrowing a p-type epitaxial layer electrically coupled to the predetermined portion of the n-type epitaxial structure.
11. The method of claim 10 wherein:
- a regrowth interface is defined by the p-type epitaxial layer and the n-type structure; and
- a p-n junction is displaced by a predetermined distance from the regrowth interface.
12. The method of claim 11 wherein the predetermined distance ranges from about 1 nm to about 1 μm.
13. The method of claim 10 wherein the predetermined portion is characterized by a depth ranging from about 1 nm to about 1 μm.
14. The method of claim 10 wherein the acceptor comprises zinc.
15. The method of claim 10 wherein the acceptor comprises at least one of magnesium, beryllium, or calcium.
16. The method of claim 10 wherein the n-type III-nitride substrate comprises a GaN substrate doped with at least one of silicon or oxygen.
17. The method of claim 10 further comprising performing an in situ etch process prior to regrowing the p-type epitaxial layer.
18. A method of fabricating a lateral p-n junction, the method comprising:
- providing a III-nitride substrate having a first conductivity type;
- forming a diffusion mask over a predetermined portion of the III-nitride substrate;
- forming a dopant source including a dopant in contact with at least an exposed portion of the III-nitride substrate; and
- diffusing the dopant into the III-nitride substrate to form a diffusion region having a second conductivity type different from the first conductivity type.
19. The method of claim 18 wherein a spatial orientation of a p-n junction between the III-nitride substrate and the diffusion region is substantially orthogonal to a growth direction of the III-nitride substrate.
20. The method of claim 18 wherein the III-nitride substrate comprises a GaN substrate doped with at least one of silicon or oxygen.
21. The method of claim 20 wherein the dopant comprises zinc.
22. The method of claim 18 wherein the dopant source comprises zinc oxide.
23. The method of claim 18 wherein the dopant source comprises a source of at least one of magnesium, beryllium, or calcium.
24. A method of forming a lateral p-n junction, the method comprising:
- providing a substrate comprising a GaN-based material characterized by a first conductivity type;
- forming a masking layer on a surface of the substrate;
- removing a predetermined portion of the substrate using an ex-situ etch process;
- removing an additional predetermined portion of the substrate using an in-situ etch process; and
- regrowing a GaN-based material characterized by a second conductivity type in at least a portion of the predetermined portion and the additional predetermined portion of the substrate.
25. The method of claim 24 wherein the substrate comprises a GaN substrate.
26. The method of claim 24 wherein the first conductivity type comprises an n-type.
27. The method of claim 26 wherein the second conductivity type comprises a p-type.
28. The method of claim 24 further comprising:
- forming an electrode on a portion of the substrate to provide an electrical connection to the GaN-based material of the first conductivity type; and
- forming a second electrode on a portion of the GaN-based material of the second conductivity type.
29. The method of claim 24 wherein a width of the predetermined portion is less than a width of the additional predetermined portion.
Type: Application
Filed: Aug 4, 2011
Publication Date: Feb 7, 2013
Patent Grant number: 9136116
Applicant: EPOWERSOFT, INC. (San Jose, CA)
Inventors: David P. Bour (Cupertino, CA), Thomas R. Prunty (Santa Clara, CA), Linda Romano (Sunnyvale, CA), Andrew P. Edwards (San Jose, CA), Isik C. Kizilyalli (San Francisco, CA), Hui Nie (Cupertino, CA), Richard J. Brown (Los Gatos, CA), Mahdan Raj (Cupertino, CA)
Application Number: 13/198,666
International Classification: H01L 29/20 (20060101); H01L 21/20 (20060101);