PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES
Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.
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This disclosure relates generally to semiconductors devices, and in particular, but not exclusively to pad structures for integrated circuits.
BACKGROUND INFORMATIONSemiconductor devices such as integrated circuits (“IC”) or chips are formed with a plurality of bonding pads on the surface, and provide an on-chip interface to electrically couple signals on the semiconductor devices to external pins off-chip. As the size of ICs decrease with advancing technology, the pad size and pitch do not decrease at the same rate. Consequently, a greater percentage of area on an IC is taken up by bonding pads and their related structures.
One drawback of the above-described bonding pad structure is that a large portion of semiconductor substrate 130 is removed to accommodate bonding pad 125. Therefore, there is a reduced amount of semiconductor substrate 130 for circuit formation. With the percentage of area of an IC taken up by bonding pads increasing, bonding pad structures capable of supporting circuits under the bonding pad are needed.
Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Embodiments of a semiconductor device and methods of manufacture for a semiconductor device are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other components, materials, etc. In other instances, well-known structures, materials or operations are not shown or described in detail to avoid obscuring certain aspects.
References throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Directional terminology such as top, bottom, down, and over are used with reference to the orientation of the figure(s) being described, but should not be interpreted as any kind of limitation on the orientation of the embodiment.
As used herein, the term “substrate” refers to any of a variety of substrates formed using semiconductor material—e.g. based upon silicon, silicon-germanium, germanium, gallium arsenide and/or the like. A substrate layer may include such a substrate and one or more structures resulting from operations that have been performed upon the substrate—e.g. such operations forming regions, junctions and/or other structures in the substrate. By way of illustration and not limitation, such structures may include one or more of doped semiconductor regions and/or undoped semiconductor regions, epitaxial layers of silicon, and other semiconductor structures formed upon the substrate.
In the illustrated embodiment, BSI image sensor 200 includes light sensitive region 210 surrounded by peripheral circuit region 220. Bonding pads (e.g. bonding pad 225) and cavities (e.g. cavity 226) may be located in peripheral circuit region 220 so that they do not block incident light from light sensitive region 210. Light sensitive region 210 may contain an image sensor pixel array. In the illustrated embodiment, cavity 226 is located on an outside perimeter of peripheral circuit region 220 to increase useable semiconductor substrate area. In other embodiments, cavity 226 is closer to light sensitive region 210 than bonding pad 225. Bonding pad 225 makes signals inside BSI image sensor 200 externally available through wire bond connection.
Cavity 226 is disposed in semiconductor substrate 230 in peripheral circuit region 220, in the illustrated embodiment. Cavity 226 may be etched in semiconductor substrate 230 or formed using a different process. Cavity 226 extends at least from the back-side of semiconductor substrate 230 to the front-side of semiconductor substrate 230. Cavity 226 may also extend through an ILD layer 240. In the illustrated embodiment, ILD layer 240 is disposed between semiconductor substrate 230 and metal stack 250. A portion of conductive layer 275 (the portion disposed at the bottom of cavity 226) connects to metal stack 250. This connection creates a conductive electrical path between bonding pad 225 and metal stack 250.
M4, a metal interconnect layer disposed on the front side of substrate 230, is illustrated as being disposed over and contacting handle substrate 260. TSV pad 285 may be included in M4 or another metal interconnect layer. TSV pad 285 may be silicon and is positioned to accept a TSV. TSV pad 285 may be positioned to distribute signals off-chip or receive off-chip signals. In one embodiment, TSV 285 pad is positioned to maximize the availability of metal interconnect layers (e.g. M1, M2, and M3) directly below bonding pad 225 in order to allow for metal interconnect layers to connect to the circuitry (e.g. peripheral circuitry 232) directly below bonding pad 225. In the illustrated embodiment, TSV 280 runs through handle substrate 260 and connects with TSV pad 285. In some embodiments, all or part of handle substrate 260 is removed from BSI image sensor 200. TSV 280 may run through a substrate other than handle substrate 260.
TSV pad 285 allows metal stack 250 and any circuitry connected to metal stack 250 (e.g. photosensitive elements 231 and peripheral circuitry 232) to be accessed from the front-side of BSI image sensor 200 by a via (e.g. TSV 280) and bonding pad 225 allows metal stack 250 to be accessed from the back-side by wire bond. Furthermore, having cavity 226 disposed on an outside perimeter of peripheral circuit region 220 allows semiconductor substrate to remain continuous for a larger area. And, since bonding pad 225 is connected to metal stack 250 by the portion of conductive layer 275 that is disposed in the cavity, circuitry under pad (“CUP”) is possible. In contrast, bonding pad 125 in conventional IC 100 requires removal of a larger portion of semiconductor substrate 130 and no CUP is possible. Hence, the illustrated embodiment allows for increased semiconductor substrate to hold circuitry while still allowing wire bond access (through bonding pad 225) and TSV access (by position of TSV pad 285). Although the illustrated embodiment is of BSI image sensor 200, the disclosure could apply to other ICs.
In process block 305, a semiconductor substrate (e.g. semiconductor substrate 230) with circuitry (e.g. peripheral circuitry 232) disposed in it is provided. In process block 310, a metal stack (e.g. metal stack 250) including a TSV pad (e.g. TSV pad 285) is formed on a second side of the semiconductor substrate. A cavity (e.g. cavity 226) is created through semiconductor substrate at process block 315. The cavity may extend past the semiconductor substrate through other layers until the cavity reaches the metal stack. The cavity may be formed using known etch processes such as dry etching. At process block 320, an insulation layer (e.g. insulation 270) is formed on a first side of the semiconductor substrate. The insulation layer may also be formed on the sidewalls of the cavity and at the bottom of the cavity. The bottom of the cavity (where the cavity connects to the metal stack) may be opposite of the first side of the semiconductor substrate. A portion of the insulation layer at the bottom of the cavity is removed at process block 325. The insulation layer at the bottom of the cavity is removed so that a conductive layer may connect with the metal stack. At process block 330, a conductive layer (which includes a bonding pad) is formed above the insulation layer and is also disposed in the cavity. The conductive layer is disposed so that the conductive layer connects to the metal stack.
After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 410 and transferred to function logic 415. Readout circuitry 410 may include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, or otherwise. Function logic 415 may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 410 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously. Control circuitry 420 is coupled to pixel array 405 to control operational characteristic of pixel array 405. For example, control circuitry 420 may generate a shutter signal for controlling image acquisition.
In
Reset transistor T2 is coupled between power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between the power rail VDD and select transistor T4. SF transistor T3 operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuitry 500 to the readout column line under control of select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry 420.
The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Claims
1. An image sensor, comprising:
- a semiconductor substrate including a light sensitive region surrounded by a peripheral circuit region;
- a cavity disposed in the peripheral circuit region of the semiconductor substrate, the cavity extending at least from a first side of the semiconductor substrate through to a second side of the semiconductor substrate;
- an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity;
- a conductive layer including a bonding pad disposed over the insulation layer and over the first side of the semiconductor substrate, wherein the conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate; and
- a through silicon via (“TSV”) pad disposed below the second side of the semiconductor substrate and connected to the metal stack, wherein the TSV pad is positioned to accept a TSV.
2. The image sensor of claim 1, further comprising:
- photosensitive elements disposed in the light sensitive region of the semiconductor substrate; and
- readout circuitry disposed under the bonding pad and disposed in the peripheral circuit region of the semiconductor substrate, wherein the readout circuitry is coupled to readout image data from the photosensitive elements.
3. The image sensor of claim 1, further comprising:
- a handle substrate disposed below the TSV pad; and
- a TSV running through the handle substrate and connecting with the TSV pad.
4. The image sensor of claim 1, further comprising:
- an inter-layer dielectric disposed between the metal stack and the semiconductor substrate, wherein the cavity extends through the inter-layer dielectric.
5. The image sensor of claim 1, further comprising:
- an anti-reflective layer disposed over photosensitive elements disposed in the light sensitive region of the semiconductor substrate.
6. The image sensor of claim 1, wherein the cavity is on an outside perimeter of the peripheral circuit region of the semiconductor substrate.
7. The image sensor of claim 1, wherein the metal stack includes a plurality of metal interconnect layers, and wherein at least a portion of the TSV pad is disposed directly below at least one metal interconnect layer in the metal stack, the at least one metal interconnect layer disposed directly below and connected to circuitry disposed directly below the bonding pad.
8. The image sensor of claim 1, wherein the entire bonding pad is disposed above and over the peripheral circuit region.
9. The image sensor of claim 1, wherein the metal stack includes the TSV pad.
10. The image sensor of claim 1, wherein the TSV pad is positioned for distributing or receiving off-chip signals.
11. A semiconductor device, comprising:
- a semiconductor substrate;
- a cavity disposed in the semiconductor substrate extending at least from a first side of the semiconductor substrate through a second side of the semiconductor substrate;
- an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity;
- a conductive layer disposed over the insulation layer and disposed in the cavity, wherein the conductive layer includes a bonding pad above the first side of the semiconductor substrate, and wherein the conductive layer connects to a metal stack at a bottom of the cavity wherein the bottom of the cavity is opposite the first side of the semiconductor substrate; and
- a through silicon via (“TSV”) pad disposed below the bottom of the semiconductor substrate and connected to the metal stack, wherein the TSV pad is positioned to accept a TSV.
12. The semiconductor device of claim 11, wherein the semiconductor device comprises an image sensor, the image sensor further comprising:
- circuitry disposed in the semiconductor substrate, wherein the circuitry is disposed under the bonding pad.
13. The semiconductor device of claim 12, wherein the cavity is on an outside perimeter of the semiconductor substrate to maximize the area of continuous semiconductor substrate.
14. The semiconductor device of claim 12, further comprising:
- a handle substrate disposed below the TSV pad; and
- a TSV running through the handle substrate and connecting with the TSV pad.
15. The semiconductor device of claim 12, further comprising:
- an inter-layer dielectric disposed between the metal stack and the semiconductor substrate, wherein the cavity extends through the inter-layer dielectric.
16. The semiconductor device of claim 12, wherein the metal stack includes a plurality of metal interconnect layers, and wherein a portion of the TSV pad is disposed directly below at least one metal interconnect layer in the metal stack, the at least one metal interconnect layer disposed directly below and connected to circuitry disposed directly below the bonding pad.
17. The semiconductor device of claim 12, wherein the TSV connects the TSV pad to an off-chip signal.
18. A method for fabricating a semiconductor device, the method comprising:
- providing a semiconductor substrate with circuitry disposed therein;
- forming a metal stack below a second side of the semiconductor substrate, wherein the metal stack includes a through silicon via (“TSV”) pad, and wherein the TSV pad is positioned to accept a TSV;
- creating a cavity through the semiconductor substrate;
- forming an insulation layer on a first side of the semiconductor substrate and on sidewalls of the cavity;
- removing a portion of the insulation layer from a bottom of the cavity, wherein the bottom of the cavity is opposite the first side of the semiconductor substrate; and
- forming a conductive layer over the insulation layer and disposed in the cavity, wherein the conductive layer forms a bonding pad above the semiconductor substrate, and wherein the conductive layer connects to the metal stack at the bottom of the cavity.
19. The method of claim 18, further comprising:
- forming a handle substrate below the TSV pad; and
- forming a TSV running through the handle substrate and connecting with the TSV pad.
20. The method of claim 18, further comprising:
- forming an inter-layer dielectric between the metal stack and the semiconductor substrate, wherein etching away the portion of the insulation layer at a bottom of the cavity includes etching away a portion of the inter-layer dielectric between the metal stack and the semiconductor substrate.
Type: Application
Filed: Nov 3, 2011
Publication Date: May 9, 2013
Patent Grant number: 8569856
Applicant: OMNIVISION TECHNOLOGIES, INC. (Santa Clara, CA)
Inventors: Yin Qian (Milpitas, CA), Hsin-Chih Tai (San Jose, CA), Keh-Chiang Ku (Cupertino, CA), Vincent Venezia (Los Gatos, CA), Duli Mao (Sunnyvale, CA), Wei Zheng (Los Gatos, CA), Howard E. Rhodes (San Martin, CA)
Application Number: 13/288,731
International Classification: H01L 31/0216 (20060101); H01L 21/768 (20060101); H01L 31/02 (20060101);