STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE
A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain.
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This is a continuation of prior U.S. patent application Ser. No. 13/652,623, filed Oct. 16, 2012.
TECHNICAL FIELDThis disclosure relates generally to the formation of a microelectromechanical systems (MEMS) device in a complementary metal oxide semiconductor (CMOS) back end of line (BEOL) process.
BACKGROUNDIn central processing unit (CPU) chips, parts of the circuit are generally put down by power gating techniques when not operated to save power. Under current technology, high threshold voltage field effect transistors (FETs) are used for the power gating. It has been found, in practice, that a considerable amount of power is wasted due to voltage drop on BEOL wiring between power gating transistors and the shut down circuit.
In accordance with the present invention, MEMS transistors are constructed in the far back end of line (FBEOL) for use instead of transistors, such as standard FETs, which cannot be built at BEOL, and can only be built at the front end of line (FEOL).
SUMMARYIn an exemplary embodiment, a MEMS transistor in a far back end of line (FBEOL) level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends, and is electrically coupled to a source for the MEMS transistor. A gate and a drain are in a sidewall of the cavity, and are separated in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit from the MEMS cantilever switch by a gap. In response to an appropriate gate signal, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain.
In another exemplary embodiment, a CMOS integrated circuit includes at least one MEMS transistor as described in the preceding paragraph.
In another exemplary embodiment, a method for fabricating a MEMS transistor in a far back end of line (FBEOL) level of a CMOS integrated circuit is disclosed. In accordance with the method, a first cavity is formed within a first oxide layer in the FBEOL level of the CMOS integrated circuit. The first cavity is then filled with a sacrificial material, such as polysilicon. The first oxide layer and first cavity are next covered with a first dielectric layer, which is then covered by a second oxide layer. Subsequently, a second cavity is formed in the first dielectric layer and the second oxide layer, and is at least in part contiguous with the first cavity. The side walls of the second cavity are then lined with the sacrificial material. A third cavity and a fourth cavity are formed next to one of the side walls of the second cavity in the first dielectric layer and the second oxide layer in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit. The sacrificial material on the side wall of the second cavity separates the second cavity from the third and fourth cavities. The second, third, and fourth cavities are filled with an electrically conducting material to form a MEMS cantilever switch, a gate, and a drain, respectively. The second cavity, including the side walls and the MEMS cantilever switch, are then covered with the sacrificial material. The second oxide layer, the sacrificial material, and the gate and the drain are next covered with a second dielectric layer, and the second dielectric layer is covered with a third oxide layer. Finally, a vent hole is provided at least through the second dielectric layer and the third oxide layer to the sacrificial material, and the sacrificial material, including the sacrificial material on the side wall of the second cavity, is removed through the vent hole with a solvent to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain, enabling it to move into contact with the drain when required.
In still another exemplary embodiment, another method for fabricating a MEMS transistor in a far back end of line (FBEOL) level of a CMOS integrated circuit is disclosed. In accordance with this method, a first cavity is formed within an oxide layer in the FBEOL level of said CMOS integrated circuit. The first cavity is then lined with a sacrificial material to form a layer of the sacrificial material therein. A second cavity and a third cavity are then formed next to one of the side walls of the first cavity in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit. The sacrificial material on the side wall of the first cavity separates the first cavity from the second and third cavities. The first, second, and third cavities are filled with an electrically conducting material to form a MEMS cantilever switch, a gate, and a drain. At least a portion of the first cavity is then covered with the sacrificial material, the portion including the MEMS cantilever switch within the first cavity. The sacrificial material is then covered with a layer of a dielectric material. A vent hole is then provided through the dielectric material to the sacrificial material, and the sacrificial material, including the sacrificial material on the side wall of the first cavity, is removed through the vent hole with a solvent to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain, enabling it to move into contact with the drain when required.
The foregoing and other aspects of these teachings are made more evident in the following detailed description, when read in conjunction with the attached drawing figures.
As noted above, the present invention generally relates to the formation of a MEMS cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of line (BEOL) process. As such, the MEMS cantilever switch of the present invention may be formed during a standard BEOL process. In
Next, as shown in
A layer 112 of an electrically conducting material is plated onto polysilicon layer 108, filling cavity 110, as shown in the cross-sectional view of
Next, a dielectric layer 114 is deposited on oxide layer 104 covering cavity 106 (previously filled with polysilicon) and cavity 110 (filled with electrically conducting material), and an oxide layer 116 is deposited on dielectric layer 114, as shown in
The structure shown in
Next, a polysilicon layer 122 is deposited onto oxide layer 116 and lines the sides and bottoms of cavities 118, 120, as shown in
Referring now to
As was done earlier in the steps shown in
Next, a polysilicon layer 126 is applied onto oxide layer 116, cavities 118, 120, 124 (all filled with electrically conducting material), and polysilicon side walls 122, and removed everywhere except over cavity 118 (filled with electrically conducting material) and side walls 122 on both sides of cavity 118, leaving the structure shown in
Turning now to
In
Referring to
To obtain the structure shown in
Next, a photoresist layer is deposited on the oxide layer 204 and polysilicon layer 210, filling cavities 206, 208, 212, and exposed to light and removed in predetermined areas. Following reactive-ion etching (RIE), a cavity 214 is formed by removing polysilicon layer 210 in cavity 206 and dielectric layer 202 to extend down to the lower BEOL layers or the FEOL layers, not shown in the figure. Cavity 214 is formed for a device manufactured during a standard BEOL process, which may proceed during the manufacture of the MEMS cantilever switch of the present invention. The structure resulting from this step is shown in
A layer of electrically conducting material is plated onto oxide layer 204, filling cavities 208, 212, 214. The layer of electrically conducting material is then removed by chemical mechanical polishing/planarization (CMP), leaving electrically conducting material in cavities 208, 212, 214, as shown in
In
Finally, in
It should be recalled that all of the preceding
By providing the MEMS cantilever switches in CMOS integrated circuits instead of the customary FETs in the far back end of line to function as power gating transistors, a noticeable benefit from an “on” resistance perspective can be obtained. For example, the “on” resistance of the MEMS transistor can be in the range from approximately 0.1 to 0.2 ohm, which is about five times lower than the “on” resistance of the FETs used for gating purposes. Moreover, leakage for the MEMS transistor will be zero, as opposed to that of the FET, which is approximately 10 μA. The latter can result in a large loss of power, as there may be thousands of such devices in a single integrated circuit.
Various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings. However, any and all modifications of the teachings of this disclosure will still fall within the scope of the non-limiting embodiments of this invention.
Although described in the context of particular embodiments, it will be apparent to those skilled in the art that a number of modifications and various changes to these teachings may occur. Thus, while the invention has been particularly shown and described with respect to one or more embodiments thereof, it will be understood by those skilled in the art that certain modifications or changes may be made therein without departing from the scope of the invention as set forth above, or from the scope of the claims to follow.
Claims
1. A MEMS (micro-electromechanical systems) transistor in a far back end of line (FBEOL) level of a CMOS (complementary metal-oxide-semiconductor) integrated circuit, said FBEOL level having a plurality of layers and being in the form of a plane over one or more lower levels of said CMOS integrated circuit, said MEMS transistor comprising:
- a cavity enclosed within said plurality of layers of said FBEOL level of said integrated circuit;
- a MEMS cantilever switch within said cavity, said MEMS cantilever switch being of a metal and having two ends and being anchored within said cavity at least at one of said two ends, said MEMS cantilever switch being electrically coupled to a source for said MEMS transistor, said MEMS cantilever switch being oriented in a direction parallel to said plane of said FBEOL level;
- a gate, said gate beings of a metal and being in a side wall of said cavity and separated from said MEMS cantilever switch, in a direction parallel to the plane of said FBEOL level of said CMOS integrated circuit, by a gap; and
- a drain, said drain being of a metal and being in said side wall of said cavity adjacent to said gate, said drain also being separated from said MEMS cantilever switch, in a direction parallel to the plane of said FBEOL level of said CMOS integrated circuit, by said gap,
- whereby, in response to a voltage applied to said gate, said MEMS cantilever switch moves across said gap in a direction parallel to the plane of said FBEOL level of said CMOS integrated circuit into electrical contact with said drain to permit a current to flow between said source and said drain.
2. A MEMS transistor as claimed in claim 1, wherein said MEMS cantilever switch is anchored within said cavity at both of said two ends.
3. A MEMS transistor as claimed in claim 1,wherein said MEMS cantilever switch has a length in a range from 1 to 10,000 micrometers (μm).
4. A MEMS transistor as claimed in claim 1, wherein said MEMS cantilever switch has a width of in a range from 10 nanometers (nm) to 100 micrometers (μm).
5. A MEMS transistor as claimed in claim 1, wherein said gap has a width in a range from 1.0 nanometer (nm) to 1.0 micrometer (μm).
6. (canceled)
7. (canceled)
8. A MEMS transistor as claimed in claim 1, wherein said metal includes at least one of aluminum, copper, and gold.
9. A CMOS (complementary metal-oxide semiconductor) integrated circuit, said CMOS integrated circuit being in the form of a plane and including at least one MEMS (micro-electromechanical systems) transistor, said MEMS transistor comprising:
- a cavity enclosed within said plurality of layers of said integrated circuit;
- MEMS cantilever switch within said cavity, said MEMS cantilever switch being of a metal and having two ends and being anchored within said cavity at least at, one of said two ends, said MEMS cantilever switch being electrically coupled to a source for said MEMS transistor, said MEMS cantilever switch being oriented in a direction parallel to said plane of said integrated circuit;
- a gate, said gate being of a metal and being in a side wail of said cavity and separated from said MEMS cantilever switch, in a direction parallel to the plane of said CMOS integrated circuit by a gap; and
- a drain, said drain being of a metal and being in said side wall of said cavity adjacent to said gate, said drain also being separated from said MEMS cantilever switch, in a direction parallel to the plane of said CMOS integrated circuit, by said gap,
- whereby, in response to a voltage applied to said gate, said MEMS cantilever switch moves across said gap in a direction parallel to the plane of said CMOS integrated circuit into electrical contact with said drain to permit a current to flow between said source and said drain.
10. A CMOS integrated circuit as claimed in claim 9, wherein said MEMS cantilever switch is anchored within said cavity at both of said two ends.
11. A CMOS integrated circuit as claimed in claim 9, wherein said MEMS cantilever switch has a length in a range from 1 to 10000 micrometers (μm),
12. A CMOS integrated circuit as claimed in claim 9, wherein said MEMS cantilever switch has a width of in a range from 10 nanometers (nm) to 100 micrometers (μm).
13. A CMOS integrated circuit as claimed in claim 9, wherein said gap has a width in a range twin 1.0 nanometer (nm) to 1.0 micrometer (μm).
14. (canceled)
15. (canceled)
16. A CMOS integrated circuit as claimed in claim 9, wherein said metal includes at least one of aluminum, copper, and gold.
17. A CMOS integrated circuit as claimed in claim 9, wherein said MEMS transistor is in a far back end of line (FBEOL) level thereof.
Type: Application
Filed: Nov 8, 2012
Publication Date: Apr 17, 2014
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Leland CHANG (New York, NY), Guy Cohen (Mohegan Lake, NY), Michael A. Guillorn (Yorktown Heights, NY), Effendi Leobandung (Wappinger Falls, NY), Fei Liu (Yorktown Heights, NY), Ghavam G. Shahidi (Pound Ridge, NY)
Application Number: 13/672,257
International Classification: H01L 29/78 (20060101);