DUAL SHALLOW TRENCH ISOLATION (STI) FIELD EFFECT TRANSISTOR (FET) AND METHODS OF FORMING
Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; an shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
Latest IBM Patents:
- AUTO-DETECTION OF OBSERVABLES AND AUTO-DISPOSITION OF ALERTS IN AN ENDPOINT DETECTION AND RESPONSE (EDR) SYSTEM USING MACHINE LEARNING
- OPTIMIZING SOURCE CODE USING CALLABLE UNIT MATCHING
- Low thermal conductivity support system for cryogenic environments
- Partial loading of media based on context
- Recast repetitive messages
The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to transistor structures in integrated circuit devices.
BACKGROUNDAs integrated circuit technologies have advanced, the size of these devices has correspondingly decreased. In particular, as devices are reduced in scale to comply with ever-smaller packaging, tighter constraints are applied to their dimensions and spacings.
In some particular devices, such as high-voltage field effect transistors (HVFETs), smaller constraints can restrict the breakdown voltage and reliability of these devices. Further, these HVFETs can be harder to reliably design and manufacture on a smaller scale.
SUMMARYVarious embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, a FET structure includes: a deep n-type well; a shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
A first aspect includes a FET structure having: a deep n-type well; a shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
A second aspect includes a method including: forming a shallow n-type well within a deep n-type well; and forming a dual-level shallow trench isolation (STI) within the shallow n-type well region, the dual-level STI including: a first section having a first depth within the n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
A third aspect includes a method including: forming a first trench in a doped substrate; forming a pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the doped substrate; forming a pad nitride over the pad oxide; forming a mask over the pad nitride to define a shallow trench isolation (STI) window; and etching the pad nitride, the pad oxide and the doped substrate to form a second trench below the first trench and connected with the first trench, the second trench having a distinct width from a width of the first trench.
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
It is noted that the drawings of the invention are not necessarily to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
DETAILED DESCRIPTIONAs noted, the subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to transistor structures in integrated circuit devices.
Various particular embodiments include a FET structure having: a deep n-type well; a shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
Various additional particular embodiments include a method including: forming a shallow n-type well within a deep n-type well; and forming a dual-level shallow trench isolation (STI) within the shallow n-type well, the dual-level STI including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
Various further particular embodiments include a method including: forming a first trench in a doped substrate; forming a pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the doped substrate; forming a pad nitride over the pad oxide; forming a mask over the pad nitride to define a shallow trench isolation (STI) window; and etching the pad nitride, the pad oxide and the doped substrate to form a second trench below the first trench and connected with the first trench, the second trench having a distinct width from a width of the first trench.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely exemplary.
It is understood that commonly labeled elements between the figures can represent substantially identical components, unless otherwise noted. Redundant description of these elements is minimized herein for the purposes of clarity.
Turning to
As shown in
In any case, the STI region 10 can include a first section 12 having a first depth (d1) within the shallow n-type well 6 as measured from an upper surface 14 of the shallow n-type well 6. The first section 12 can be formed of a conventional STI material, e.g., silicon oxide. The STI region 10 can also include a second section 16 contacting and overlying the first section 12. The second section can have a second depth (d2) within the n-type well as measured from the upper surface 14 of the shallow n-type well 6. That is, according to various embodiments, the FET structure 2 (as well as other FET structures shown and described herein) can include an STI region (e.g., STI region 10) that has two distinct sub-regions having distinct depths. The FET structure 2 can include a polysilicon gate layer 15, overlying the STI region 10 and extending from the p-type well to the n-type well.
In various embodiments, the second section 16 has a greater width (w2) than the first section 12 (w1), e.g., as shown in
In various other embodiments, for example, in the FET structure 22 shown in
In various embodiments, the first trench 70 and the second trench 88 collectively form a stepped surface 90. The stepped surface 90 can later form the foundation of a stepped STI, as described herein. Further, as described herein, the stepped surface 90 can be rounded, beveled or otherwise at least partially arced in order to form one or more of the STI structures shown and described herein.
In various other embodiments, a method of forming a FET structure can include:
Process PA: forming a shallow n-type well within a deep n-type well; and
Process PB: forming a dual-level shallow trench isolation (STI) within the shallow n-type well region. In some embodiments, the dual-level STI can include: a) a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and b) a second section contacting and overlying the first section. The second section can have a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
In various embodiments, the process of forming of the dual-level STI within the shallow n-type well region includes:
(i) etching the shallow n-type well within the deep n-type layer to form a first trench having a first width;
(ii) forming a pad oxide over the shallow n-type well including the first trench; and
(iii) forming a pad nitride over the pad oxide.
In some cases, the process of forming the dual-level STI further includes:
(iv) forming a mask over the pad nitride; and
(v) etching the pad nitride, the pad oxide, and the shallow n-type well within the deep n-type well to form a second trench above the first trench. As described herein, the second trench can have a second width distinct from the first width.
In some cases, the process of forming the pad oxide (ii) includes forming the pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the shallow n-type well.
In some cases, the process of forming the pad nitride (iii) includes forming the pad oxide to substantially cover the pad oxide.
As used herein, the term “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
When an element or layer is referred to as being “on”, “engaged to”, “connected to” or “coupled to” another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly engaged to”, “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Spatially relative terms, such as “inner,” “outer,” “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is further understood that the terms “front” and “back” are not intended to be limiting and are intended to be interchangeable where appropriate.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the invention as defined by the accompanying claims.
Claims
1. A field effect transistor (FET) structure, comprising:
- a deep n-type well;
- a shallow n-type well and a p-type well each within the deep n-type well; and
- a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.
2. The FET structure of claim 1, wherein the second section includes a zero-level mask material.
3. The FET structure of claim 2, wherein the second section has a greater width than the first section.
4. The FET structure of claim 2, wherein the second section includes a portion extending above the shallow n-type well.
5. The FET structure of claim 1, wherein the second section extends laterally beyond the first section within the shallow n-type well.
6. The FET structure of claim 5, wherein a portion of the first section includes an upper surface that is coplanar with an upper surface of the second section.
7. The FET structure of claim 1, further comprising a contact layer overlying the STI region and extending from the p-type well to the shallow n-type well.
8. The FET structure of claim 1, further comprising a substrate, wherein the deep n-type well overlies the substrate.
9. The FET structure of claim 1, wherein the FET structure includes a high-voltage complementary metal oxide semiconductor (HVCMOS) FET structure.
10. The FET structure of claim 1, wherein the second section includes a substantially rounded profile proximate at least one lateral edge thereof.
11. A method comprising:
- forming a shallow n-type well within a deep n-type well; and
- forming a dual-level shallow trench isolation (STI) within the shallow n-type well, the dual-level STI including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the p-type well as measured from the upper surface of the shallow n-type well.
12. The method of claim 11, wherein the forming of the dual-level STI within the shallow n-type well region includes:
- etching the shallow n-type well within the deep n-type well to form a first trench having a first width;
- forming a pad oxide over the shallow n-type well including the first trench; and
- forming a pad nitride over the pad oxide.
13. The method of claim 12, wherein the forming of the dual-level STI further includes:
- forming a mask over the pad nitride; and
- etching the pad nitride, the pad oxide, and the shallow n-type well within the deep n-type well layer to form a second trench above the first trench, the second trench having a second width distinct from the first width.
14. The method of claim 12, wherein the forming of the pad oxide includes forming the pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the shallow n-type well.
15. The method of claim 14, wherein the forming of the pad nitride includes forming the pad oxide to substantially cover the pad oxide.
16. A method comprising:
- forming a first trench in a doped substrate;
- forming a pad oxide over a bottom of the first trench, sidewalls of the first trench, and an upper surface of the doped substrate;
- forming a pad nitride over the pad oxide;
- forming a mask over the pad nitride to define a shallow trench isolation (STI) window; and
- etching the pad nitride, the pad oxide and the doped substrate to form a second trench below the first trench and connected with the first trench, the second trench having a distinct width from a width of the first trench.
17. The method of claim 16, wherein the forming of the pad nitride includes depositing the pad nitride to cover the pad oxide over the bottom of the first trench, sidewalls of the first trench and the upper surface of the doped substrate.
18. The method of claim 16, wherein the forming of the mask over the pad nitride includes depositing the mask over the pad nitride and exposing the mask to define the STI window.
19. The method of claim 16, wherein the first trench and the second trench collectively form a stepped surface.
20. The method of claim 16, wherein the STI window has a width substantially equal to the width of the second trench.
Type: Application
Filed: May 1, 2013
Publication Date: Nov 6, 2014
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Natalie B. Feilchenfeld (Jericho, VT), Max G. Levy (Essex Junction, VT), Richard A. Phelps (Colchester, VT), Santosh Sharma (Essex Junction, VT), Yun Shi (South Burlington, VT), Michael J. Zierak (Colchester, VT)
Application Number: 13/874,922
International Classification: H01L 29/06 (20060101); H01L 21/762 (20060101);