Forming a non-planar transistor having a quantum well channel

- Intel

In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

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Description

This application is a divisional of U.S. patent application Ser. No. 13/046,061, filed Mar. 11, 2011 now U.S. Pat. No. 8,237,153 , which is a continuation of U.S. patent application Ser. No. 11/728,891, filed Mar. 27, 2007, now U.S. Pat. No. 7,928,426, issued on Apr. 19, 2011, the content of which is hereby incorporated by reference.

BACKGROUND

A variety of electronic and optoelectronic devices can be enabled by developing thin film relaxed lattice constant III-V semiconductors on elemental silicon (Si) substrates. Surface layers capable of achieving the performance advantages of III-V materials may host a variety of high performance electronic devices such as complementary metal oxide semiconductor (CMOS) and quantum well (QW) transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb), indium gallium arsenide (InGaAs) and indium arsenide (InAs). While such high mobility QW channels have been incorporated into planar transistors, they have not been incorporated into non-planar transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section view of a device structure in accordance with an embodiment of the present invention.

FIG. 2 is a band diagram of a structure in accordance with an embodiment of the present invention.

FIG. 3 is a flow diagram of a method in accordance with an embodiment of the present invention.

 DETAILED DESCRIPTION

In various embodiments, a high-mobility strained quantum well (QW) channel may be incorporated into a non-planar structure such as a non-planar metal oxide semiconductor field effect transistor (MOSFET). Such non-planar transistors include a silicon structure or fin formed on an underlying-oxide layer, and in turn a gate structure can be formed around the silicon fin. In this way, high mobility channels with excellent electrostatic control can be achieved for ultimate channel length scalability. Furthermore, tensile and compressive strain may be simultaneously introduced to respectively optimize electron transport in silicon for n-channel MOSFETs (NMOS) and hole transport in germanium (Ge) for p-channel MOSFETs (PMOS) using a common material core. Furthermore, correct and sufficient conduction and valence band offsets provide for electron and hole confinement. Using embodiments, transistor devices may be formed using conventional stack engineering, as an outermost core layer may be formed of silicon to allow formation of a gate stack thereon.

Referring now to FIG. 1, shown is a cross section view of a device structure 10 in accordance with an embodiment of the present invention. As shown in FIG. 1, structure 10 may be used to form NMOS or PMOS devices on a substrate 30. In various embodiments, substrate 30 may be a high resistivity n or p-type (100) off-oriented Si substrate, although the scope of the present invention is not limited in this regard. As shown in FIG. 1, next a buried oxide layer 34 may be formed on substrate 30. In various embodiments, buried oxide layer 34 may be formed of a suitable oxide material such as silicon dioxide (SiO2) or other oxide.

Still referring to FIG. 1, next a silicon on insulator (SOI) layer may be formed. Specifically, a SOI layer may be deposited (or bonded) and patterned to obtain a SOI core 40, which is a non-planar structure on buried oxide layer 34. Note this SOI core is formed of a silicon fin or narrow strip that has a width much less than the extent of buried oxide layer 34. Note, this layer may also be strained. As shown in FIG. 1, a compressive strained QW layer 42 may be wrapped around SOI core 40. In various embodiments, QW layer 42 may be a Ge layer selectively grown on SOI core 40. The growth may be conducted by vapor deposition method and thickness can range from 1 nanometers (nm)-20 nm. Next, a tensile strained Si layer 44 may be formed on QW layer 42. In various embodiments, Si layer 44 may be selectively grown to wrap around QW layer 42. The growth may be conducted by vapor deposition method and thickness can range from 1 nm-20 nm. Using this configuration, holes (electrons) may travel and be confined within QW layer 42 for high mobility conduction.

Referring still to FIG. 1, next a gate dielectric layer 46 may be formed over Si layer 44. In various embodiments, a conformal gate dielectric layer may be formed using an atomic layer deposition (ALD) to thus wrap around the core formed of Si/Ge/SOI. In various embodiments, gate dielectric layer 46 may be formed using a low dielectric constant (low-k) material such as a carbon doped oxide or other such dielectric. Over gate dielectric layer 46, a gate electrode layer 48 may be formed. In various embodiments, an ALD process may be used to form conformal gate electrode layer 48. Note that in various embodiments, similar or different electrode materials may be used for n-channel and p-channel MOSFETs.

While shown with this particular implementation in the embodiment of FIG. 1, the scope of the present invention is not limited in this regard. For example, in other embodiments a bulk Si substrate may be used with appropriate isolation to form the Si core (i.e., over a given SOI substrate). Furthermore, instead of a QW layer formed of pure Ge, a QW layer may be formed using high Ge content silicon germanium (SiGe) with compressive strain. In various embodiments, the Ge concentration may be between approximately 10% and 100%. In this way, thicker QWs may be realized for particular applications. While not shown in FIG. 1, a fully completed device may further include source and drain electrodes formed of a contact layer. For an NMOS device, the contact layer may be n+doped, while for a PMOS device, the contact layer may be p+doped.

Accordingly, in various embodiments non-planar transistor devices may be formed using a high mobility material to form high electron mobility transistors (HEMTs) or high hole mobility transistors (HHMTs) or high hole mobility transistors (HHMTs) having high speed and low power consumption. Such devices may have dimensions less than approximately 50 nm with a switching frequency of approximately 562 gigahertz (GHz). Such devices may be able to operate at between approximately 0.5-1.0 volts without significant reduction of drive current. Furthermore, embodiments may provide lower gate delay at a gate length than a silicon based device.

Referring now to FIG. 2, shown is a band diagram of a structure in accordance with an embodiment of the present invention. As shown in FIG. 2, the band diagram illustrates, via the top line a conduction band (i.e., Ec) and via the lower line a valence band (i.e., Ev). Beginning at the left-hand side of FIG. 2, the SOI layer, which may be pure silicon, is formed. Over this layer, a QW layer, which may be formed of compressive strain germanium or silicon germanium (SiGe) may be formed. The QW channel layer may be formed having a smaller bandgap than the SOI core. Over the QW channel layer, an upper tensile strained silicon layer may be formed that may, in some embodiments have a smaller bandgap than the SOI core, but a layer bandgap than the QW channel layer. Then, as shown in FIG. 2, a dielectric layer may be formed over the silicon layer which has a larger bandgap than the other layers. As shown in FIG. 2, the Ge layer provides a QW for holes and the Si layer provides the QW for electrons.

Referring now to FIG. 3, shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown in FIG. 3, method 100 may begin by forming a buried oxide layer over a Si substrate (block 110). Next, a SOI core may be formed over the buried oxide layer (block 120). For example, a silicon layer may be deposited (or bonded) and patterned to form the SOI core. Then a QW layer may be wrapped around the SOI core (block 130). For example, in one embodiment a strained compressive Ge or SiGe layer may be grown on the SOI core. Above the QW layer, an Si layer may be formed to wrap around the QW layer (block 140). Then a gate stack may be formed over the structure, including a dielectric layer and a gate electrode (block 150). In various embodiments, ALD processes may be performed to obtain a conformal gate dielectric layer and a conformal gate electrode. In this way, a non-planar transistor having high mobility may be formed.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

1. A method comprising:

forming a buried oxide layer directly on a substrate;
forming a non-planar silicon on insulator (SOI) core directly on the buried oxide layer, the non-planar SOI core formed of a silicon fin on the buried oxide layer;
forming a quantum well (QW) layer directly around the non-planar SOI core, wherein the QW layer is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%, wherein the QW layer is compressive strained and having a smaller bandgap than the SOI core;
forming a silicon layer around the QW layer; and
the silicon layer having a smaller bandgap than the SOI core and a larger bandgap than the QW layer.

2. The method of claim 1, further comprising:

forming a gate dielectric layer over the silicon layer; and
forming a gate electrode layer over the gate dielectric layer.

3. The method of claim 1, further comprising forming a non-planar transistor, wherein the quantum well layer comprises a channel of the non-planar transistor.

4. The method of claim 1, further comprising forming a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT).

5. The method of claim 1, further comprising forming the silicon fin having a width much less than a width of the buried oxide layer.

6. The method of claim 1, wherein the non-planar SOI core is strained.

7. The method of claim 1, wherein the silicon layer is tensile strained.

8. The method of claim 1, wherein forming the QW layer includes depositing the QW layer directly on the non-planar SOI core and at least a portion of the buried oxide layer not including the silicon fin.

9. A method comprising:

forming a buried oxide layer including silicon dioxide directly on a substrate;
forming a non-planar silicon on insulator (SOI) core directly on the buried oxide layer, the non-planar SOI core formed of a silicon fin on the buried oxide layer having a width much less than an extent of the buried oxide layer;
forming a quantum well (QW) layer directly around the non-planar SOI core, wherein the QW layer is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%, wherein the QW layer is compressive strained and having a smaller bandgap than the non-planar SOI core;
forming a silicon layer around the QW layer; and
the silicon layer having a smaller bandgap than the SOI core and a larger bandgap than the QW layer.

10. The method of claim 9, further comprising:

forming a gate dielectric layer over the silicon layer; and
forming a gate electrode layer over the gate dielectric layer.

11. The method of claim 9, further comprising forming a non-planar transistor, wherein the quantum well layer comprises a channel of the non-planar transistor.

12. The method of claim 9, further comprising forming a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT).

13. The method of claim 9, wherein forming the QW layer includes vapor deposition.

14. The method of claim 9, wherein forming the silicon layer includes vapor deposition.

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Patent History
Patent number: 8921830
Type: Grant
Filed: May 2, 2012
Date of Patent: Dec 30, 2014
Patent Publication Number: 20120211726
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Chi On Chui (Los Angeles, CA), Prashant Majhi (Austin, TX), Wilman Tsai (Saratoga, CA), Jack T. Kavalieros (Portland, OR)
Primary Examiner: Tony Tran
Application Number: 13/461,962
Classifications
Current U.S. Class: Field Effect Device (257/24); With An Insulated Gate (epo) (257/E21.409)
International Classification: H01L 29/78 (20060101); H01L 29/10 (20060101); H01L 29/66 (20060101); H01L 29/778 (20060101);