Process tube for manufacturing semiconductor wafers
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The broken lines are shown for illustrative purpose only and form no part of the claimed design.
Claims
The ornamental design for a process tub for manufacturing semiconductor wafers, as shown and described.
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Type: Grant
Filed: Mar 9, 2007
Date of Patent: Sep 22, 2009
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Hiroyuki Matsuura (Tokyo), Koichi Shimada (Tokyo)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/273,613