Process tube for manufacturing semiconductor wafers

- Tokyo Electron Limited
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Description

FIG. 1 is a perspective view of the design for a process tube for manufacturing semiconductor wafers in accordance with the invention;

FIG. 2 is a front view thereof;

FIG. 3 is a rear view thereof;

FIG. 4 is a top view thereof;

FIG. 5 is a bottom view thereof;

FIG. 6 is a right side view thereof;

FIG. 7 is a left side view thereof;

FIG. 8 is a sectional view thereof along line 88 of FIG. 4;

FIG. 9 is a sectional view thereof along line 99 of FIG. 4;

FIG. 10 is a sectional view thereof along line 1010 of FIG. 4; and,

FIG. 11 is a sectional view thereof along line 1111 of FIG. 2.

The broken lines are shown for illustrative purpose only and form no part of the claimed design.

Claims

The ornamental design for a process tub for manufacturing semiconductor wafers, as shown and described.

Referenced Cited
U.S. Patent Documents
5618349 April 8, 1997 Yuuki
D404368 January 19, 1999 Shimazu
D405062 February 2, 1999 Shimazu
D406113 February 23, 1999 Hanagata et al.
5948300 September 7, 1999 Gero et al.
6251189 June 26, 2001 Odake et al.
6538237 March 25, 2003 Yang et al.
D520467 May 9, 2006 Ishii et al.
D521464 May 23, 2006 Ishii et al.
20020014483 February 7, 2002 Suzuki et al.
Patent History
Patent number: D600659
Type: Grant
Filed: Mar 9, 2007
Date of Patent: Sep 22, 2009
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Hiroyuki Matsuura (Tokyo), Koichi Shimada (Tokyo)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/273,613