Top plate for reactor for manufacturing semiconductor
Latest Tokyo Electron Limited Patents:
- SUBSTRATE PROCESSING METHOD
- SUBSTRATE PROCESSING APPARATUS AND COOLING METHOD
- SUBSTRATE PROCESSING APPARATUS, TEMPERATURE CONTROL DEVICE, AND TEMPERATURE CONTROL METHOD
- SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM
- LOCALIZED WAFER PRE-COOLING FOR HYPERSPECTRAL IMAGING SYSTEM AND METHOD FOR THREE-DIMENSION (3D) DEFECT ANALYSIS IN WAFERS
Description
Claims
The ornamental design for top plate for reactor for manufacturing semiconductor, as shown and described.
Referenced Cited
Patent History
Patent number: D655257
Type: Grant
Filed: Apr 13, 2011
Date of Patent: Mar 6, 2012
Assignee: Tokyo Electron Limited (Minato-Ku)
Inventors: Manabu Honma (Oshu), Katsuyuki Hishiya (Oshu)
Primary Examiner: Selina Sikder
Attorney: Burr & Brown
Application Number: 29/389,553
Type: Grant
Filed: Apr 13, 2011
Date of Patent: Mar 6, 2012
Assignee: Tokyo Electron Limited (Minato-Ku)
Inventors: Manabu Honma (Oshu), Katsuyuki Hishiya (Oshu)
Primary Examiner: Selina Sikder
Attorney: Burr & Brown
Application Number: 29/389,553
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)