Semiconductor device
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Description
The broken lines shown in the drawings represent portions of the semiconductor device that form no part of the claimed design.
Claims
The ornamental design for a semiconductor device, as shown and described.
Referenced Cited
U.S. Patent Documents
Other references
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- Yoshinari Ikeda et al.—Investigation on Wirebond-less Power Module Structure with High-Density packaging and High Reliability; Proceedings of the 23rd International Symposium on Power Semiconductor Devices & IC's, May 23, 2011 San Diego, CA; pp. 272-275.
- Masafumi Norio et al.—New Power Module Structure with Low Thermal Impedance and High Reliability for SiC Devices; PCIM Europe 2011, May 11, 2011, Nuremberg, Germany; pp. 229-234.
- N. Nashida et al.—New Power Module Structure with High Power Density and High Reliability for SiC Devices-Sep. 8, 2011, pp. 233-236.
- Masafumi Norio et al.—Packaging Technologies for SiC Power Modules—vol. 84 No. 5 Nov. 10, 2011—pp. 5.
- e-Front runners—Development of New-Generation Power Semiconductor SiC Module—Sep. 29, 2010—p. 1.
- e-Front runners—Three Year Rolling Plan Power Semiconductor Business Strategy—Nov. 17, 2011—pp. 1-21.
Patent History
Patent number: D689833
Type: Grant
Filed: Nov 18, 2011
Date of Patent: Sep 17, 2013
Assignee: Fuji Electric Co., Ltd. (Kanagawa)
Inventors: Motohito Hori (Kanagawa), Tatsuo Nishizawa (Kanagawa), Yoshinari Ikeda (Kanagawa), Eiji Mochizuki (Kanagawa)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/406,718
Type: Grant
Filed: Nov 18, 2011
Date of Patent: Sep 17, 2013
Assignee: Fuji Electric Co., Ltd. (Kanagawa)
Inventors: Motohito Hori (Kanagawa), Tatsuo Nishizawa (Kanagawa), Yoshinari Ikeda (Kanagawa), Eiji Mochizuki (Kanagawa)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/406,718
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)