Semiconductor device

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Description

FIG. 1 is a front, top, right side perspective view of a semiconductor device showing our new design;

FIG. 2 is a front view thereof;

FIG. 3 is a rear view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a left side view thereof;

FIG. 7 is a right side view thereof; and,

FIG. 8 is a cross sectional view taken along line 8-8 of FIG. 4.

The broken lines shown in the drawings represent portions of the semiconductor device that form no part of the claimed design.

Claims

The ornamental design for a semiconductor device, as shown and described.

Referenced Cited
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Other references
  • Yoshinari Ikeda et al.—Investigation on Wirebond-less Power Module Structure with High-Density packaging and High Reliability; Proceedings of the 23rd International Symposium on Power Semiconductor Devices & IC's, May 23, 2011 San Diego, CA; pp. 272-275.
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Patent History
Patent number: D689833
Type: Grant
Filed: Nov 18, 2011
Date of Patent: Sep 17, 2013
Assignee: Fuji Electric Co., Ltd. (Kanagawa)
Inventors: Motohito Hori (Kanagawa), Tatsuo Nishizawa (Kanagawa), Yoshinari Ikeda (Kanagawa), Eiji Mochizuki (Kanagawa)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/406,718