Arm for wafer transportation for manufacturing semiconductor
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Description
The broken lines shown in the drawings represent portions of the arm for wafer transportation for manufacturing semiconductor that form no part of the claimed design.
Claims
The ornamental design for arm for wafer transportation for manufacturing semiconductor, as shown and described.
Referenced Cited
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Patent History
Patent number: D695240
Type: Grant
Filed: Mar 2, 2012
Date of Patent: Dec 10, 2013
Assignee: Tokyo Electron Limited (Minato-Ku)
Inventors: Naruaki Iida (Koshi), Hideki Kajiwara (Koshi)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/414,720
Type: Grant
Filed: Mar 2, 2012
Date of Patent: Dec 10, 2013
Assignee: Tokyo Electron Limited (Minato-Ku)
Inventors: Naruaki Iida (Koshi), Hideki Kajiwara (Koshi)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/414,720
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)