Abstract: A method of forming (and apparatus for forming) a layer, such as a strontium titanate, barium titanate, or barium-strontium titanate layer, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.

Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

Abstract: Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.

Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.

Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).

Abstract: A manufacturing method for a buried insulating layer-type semiconductor silicon carbide substrate comprises the step of placing an SOI substrate 100, which has a surface silicon layer 130 of a predetermined thickness and a buried insulator 120, in a heating furnace 200 and of increasing the temperature of the atmosphere within heating furnace 200 while supplying a mixed gas (G1+G2) of a hydrogen gas G1 and of a hydrocarbon gas G2 into heating furnace 200, thereby, of metamorphosing surface silicon layer 130 of SOI substrate 100 into a single crystal silicon carbide thin film 140.

Abstract: Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA layer (used as an ARC and/or hardmask) with etch selectivity to the patterned photoresist, and etching to pattern transfer through a dielectric layer of nitride. This is accomplished by oxidizing a TERA layer after etching pattern transfer through the TERA layer to form an oxidized TERA layer having chemical properties similar to oxide. The methods provide all of the advantages of the TERA material and allows for high etch selectivity (approximately 5–10:1) for etching to pattern transfer through nitride. In addition, the methodology reduces LER and allows for trimming despite reduced photoresist thickness.

Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing etching of a substrate and then depositing the film. The etching step creates nucleation sites on the substrate for the film deposition process. With this process patterning of the emitting film is avoided. A field emitter device can be manufactured with such a film.

Abstract: A substrate is polished and made an inclined substrate, which is exposed to a hydrogen plasma and is thereby smoothened. The substrate is then heated controlledly until it surface temperature reaches 830° C. Meanwhile, a gas mixture of 1% methane, 50 ppm hydrogen sulfide and hydrogen is introduced in a tubular reaction vessel to flow therethrough at 200 ml/min, where microwave plasma is excited to cause n-type semiconductor diamond to epitaxially grow on the substrate. An ion doped n-type semiconductor is thus formed that has a single donor level of an activation energy at 0.38 eV and is high in mobility and of high quality.

Abstract: The present invention relates a method for epitaxial growth of a second group III-V crystal having a second lattice constant over a first group III-V crystal having a first lattice constant, wherein strain relaxation associated with lattice-mismatched epitaxy is suppressed and thus dislocation defects do not form. In the first step, the surface of the first group III-V crystal (substrate) is cleansed by desorption of surface oxides. In the second step, a layer of condensed group-V species is condensed on the surface of the first group III-V crystal. In the third step, a mono-layer of constituent group-III atoms is deposited over the layer of condensed group-V species in order for the layer of constituent group-III atoms to retain the condensed group-V layer. Subsequently, the mono-layer of group-III atoms is annealed at a higher temperature.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse the nickel element concentrated locally. After that, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film 106 is formed in this step. At this time, the nickel element is gettered to the thermal oxide film 106. Then, the thermal oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

Abstract: Atomic layer deposition is used to provide a solid film on a plurality of disc shaped substrates. The substrates are entered spaced apart in a boat, in a furnace and heated to deposition temperature. In the furnace the substrate is exposed to alternating and sequential pulses of at least two mutually reactive reactants, in such way that the deposition temperature is high enough to prevent condensation of the at least two reactants on the surface but not high enough to result in significant thermal decomposition of each of the at least two reactants individually.

Abstract: A method of forming a three-dimensional (3D) complete photonic bandgap crystal by crystal modification is disclosed. The 3D crystal includes a first periodic array of unit cells formed from first voids connected by imaginary bonds. The first periodic array forms an incomplete bandgap. The first voids may be formed in any one of a number of shapes, including spherical. The 3D crystal further includes a second periodic array of second voids. The second voids are arranged along the imaginary bonds so as to modify each unit cell. The modification of the unit cells is designed to form a complete photonic bandgap.

Abstract: A method of growing a thin film onto a substrate placed in a reaction chamber according to the ALD method by subjecting the substrate to alternate and successive surface reactions. The method includes providing a first reactant source and providing an inactive gas source. A first reactant is fed from the first reactant source in the form of repeated alternating pulses to a reaction chamber via a first conduit. The first reactant is allowed to react with the surface of the substrate in the reaction chamber. Inactive gas is fed from the inactive gas source into the first conduit via a second conduit that is connected to the first conduit at a first connection point so as to create a gas phase barrier between the repeated alternating pulses of the first reactant entering the reaction chamber. The inactive gas is withdrawn from said first conduit via a third conduit connected to the first conduit at a second connection point.

Abstract: A CVD method deposits conformal metal layers on small features of a substrate surface. The method includes three principal operations: depositing a thin conformal layer of precursor over some or all of the substrate surface; oxidizing the precursor to convert it to a conformal layer of metal oxide; and reducing some or all of the metal oxide to convert it to a conformal layer of the metal itself. The conformal layer of precursor may form a “monolayer” on the substrate surface. Examples of metals for deposition include copper, cobalt, ruthenium, indium, and rhodium.

Abstract: A device substrate is provided having: a Si(111) substrate; a buffer layer formed by epitaxial growth on the Si(111) substrate 11, and containing at least one of a rare earth metal oxide and an alkali earth metal oxide; and a semiconductor material layer formed by epitaxial growth on the buffer layer, and containing at least one of a group II–VI semiconductor material having a wurtzite structure and a group III–V semiconductor material having a wurtzite structure. The buffer layer preferably comprises a hexagonal crystal structure oriented in the (001) plane or a cubic crystal structure oriented in the (111) plane, and the semiconductor material layer preferably comprises a hexagonal crystal structure oriented in the (001) plane.

Abstract: A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.

Abstract: In a semiconductor element comprising microcrystalline semiconductor, a semiconductor junction is provided within a microcrystal grain. Further, in a semiconductor element comprising microcrystalline semiconductor, microcrystal grains of different grain diameters are provided as a mixture to form a semiconductor layer. Thereby, discontinuity of a semiconductor junction is lessened to thereby improve the characteristics, durability, and heat resisting properties of a semiconductor element. Distortion in a semiconductor layer is also reduced.

Abstract: A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor layer formed on recess portions of the substrate and the mask layer and a nitride-based semiconductor element layer, formed on the first nitride-based semiconductor layer, having an element region. Thus, the first nitride-based semiconductor layer having low dislocation density is readily formed on the projection portions of the substrate and the mask layer through the mask layer serving for selective growth.

Abstract: The invention relates to multi-layer articles and methods of making such articles. The methods include first conditioning the surface of an underlying layer, such as a buffer layer or a superconductor layer, then disposing a layer of material on the conditioned surface. The conditioned surface can be a high quality surface. Superconductor articles formed by these methods can exhibit relatively high critical current densities.

Abstract: A method of forming a free-standing (Al, Ga, In)N article, by the steps including: providing an expitaxially compatible sacrificial template; depositing single crystal (Al, Ga, In)N material on the template to form a composite sacrificial template/(Al, Ga, In)N article including an interface between the sacrificial template and the (Al, Ga, In)N material; and interfacially modifying the composite sacrificial template/(Al, Ga, In)N article to part the sacrificial template from the (Al, Ga, In)N material and yield the free-standing (Al, Ga, In)N article. The free-standing (Al, Ga, In)N article produced by such method is of superior morphological character, and suitable for use as a substrate, e.g., for fabrication of microelectronic and/or optoelectronic devices and device precursor structures.

Abstract: A method for forming a double density wordline. A semiconductor substrate having a poly layer, a first insulating layer, a first dummy poly layer, and a second insulating layer is provided. The second insulating layer and the first dummy poly layer separated by an opening are a first wordline mask and a second wordline mask respectively. A spacer is formed on a sidewall of the opening, and the opening is filled with a second dummy poly layer. The spacer, the second insulating layer, and the exposed first insulating layer are removed to form a third wordline mask, the third wordline is composed of the second dummy poly layer and the unexposed first insulating layer. The poly layer is etched to form a first wordline, a second wordline, and a third wordline using the first wordline mask, the second wordline mask, and the third wordline mask as etching masks.

Abstract: The invention relates to a method for improving the efficiency of epitaxially grown quantum dot semiconductor components having at least one quantum dot layer. The efficiency of semiconductor components containing an active medium consisting of quantum dots is often significantly below the theoretically possible values. The inventive method enables the efficiency of the relevant component to be clearly increased without substantially changing the growth parameters of the various epitaxial layers. In order to improve the efficiency of the component, the crystal is morphologically changed when the growth of the component is interrupted at the point in the overall process at which the quantum dots of a layer have just been covered. The growth front is smoothed at the same time, leading to, for example, a reduction in waveguide loss as the thickness of the waveguide is more homogeneous if the relevant component has one such waveguide.

Abstract: A method for manufacturing a semiconductor using a wafer carrier, wherein the temperature of a wafer can be made uniform with few differences in surface composition distribution. A plurality of grooves are formed at the bottom of a wafer pocket of a wafer carrier, to make uniform the temperature of the wafer surface by diffusing heat. The grooves are deeper at the peripheral part of the wafer than at the central part, and groove density is higher at the peripheral part than at the central part. The groove patterns may include a plurality of wedge-shaped grooves widening from the central part toward the peripheral part, a plurality of circular grooves with narrowing interval therebetween from the central part toward the peripheral part, circular grooves with the diameter shortened from the central part toward the peripheral part, and square grooves with shortened sides from the central part toward the peripheral part.

Abstract: The present invention deals with the generation of sharp single crystal diamond tips and the arrays of these tips, and their fabrication technology. The invention combines the deposition of synthetic diamond films with reactive etching processes. Upon the diamond orientation prepared and reactive etching environment with considerable directivity of ions, single crystal diamond tips with different apical angles can be fabricated. Very sharp diamond tips with an apical angle of no more than about 28° and a tip radius smaller than 50 nm are fabricated on pyramidal-shaped [001]-textured diamond films by subsequent reactive etching., The technology is based on selective etching of sp2- and sp3- hybridized carbons by the activated constituents of an etching environment, in particular based on atomic hydrogen, in a way similar to ion bombardment, which contributes to overall etching and local conversion of diamond to graphitic phase promoting further etching with chemically activated species.

Abstract: A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRmax of less than or equal to 0.13 ?m and a maximum density of 0.14 scattered light centers per cm2. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 ?m×1 ?m reference area. Furthermore, there is a process for producing the semiconductor wafer.

Abstract: A method of producing a semiconductor device which removes catalyst elements from a silicon-containing semiconductor film while maintaining the advantage of low temperature process is provided. The method comprises the steps of: forming an amorphous semiconductor film containing silicon on a glass substrate to crystallize it by using a catalyst element; selectively introducing into the amorphous semiconductor film an impurity belonging to Group 15 to form gettering regions and regions to be gettered; and causing the catalyst element in the silicon film to move to the gettering regions by heat treatment. Through the gettering process, the crystalline silicon film can be obtained in which the concentration of nickel contained therein is sufficiently reduced.

Abstract: In a semiconductor manufacturing system for manufacturing compound semiconductor by MOCVD, a lead-in member is provided for guiding feed gas supplied from a feed gas supply unit onto the surface of a semiconductor substrate disposed in a reactor, a main body of the lead-in member is constituted as a hollow member to form a feed gas guide passage for conducting the feed gas in an prescribed direction and is formed with multiple orifices, and the feed gas in the feed gas guide passage is jetted from the orifices in a direction perpendicular to the prescribed direction so that the semiconductor substrate is bathed in a feed gas flow of uniform amount jetted from the lead-in member in this manner. Furthermore, a pressure differential produced between the inner side and outer side of the nozzle member enables the feed gas jetted from the nozzle member to flow over the whole surface of the substrate at a uniform flow rate.

Abstract: A method for simultaneous deposition of multiple compounds on a substrate is provided. In one aspect, a gas stream is introduced into a processing chamber and flows across a substrate surface disposed therein. The gas stream includes at least one dose of a first compound and at least one dose of a second compound. The doses of the first and second compounds are separated by a time delay, and the at least one dose of the first compound and the at least one dose of the second compound are simultaneously in fluid communication with the substrate surface.

Abstract: A method of preparing a surface of a substrate for bonding by removing oxide and altering the atomic surface of the substrate is described. The method comprises, providing a substrate comprised of a plurality of elements. The substrate is held at an elevated temperature and an over-pressure of gas is allowed to flow over the surface of the substrate. The gas over-pressure is comprised of an element found in the plurality of elements. Holding the substrate at an elevated temperature helps removes essentially all the oxide on the surface of the substrate. However, the elevated temperatures also evaporate certain atoms on the substrate surface and cause other atoms on the substrate surface to migrate. Flowing a gas over the surface of the substrate, helps to replace the atoms which have evaporated thereby preventing movement of other atoms. After removing the oxide, the substrate is allowed to cool.

Abstract: Methods are disclosed that provide for structures and techniques for the fabrication of ordered arrangements of crystallographically determined nanometer scale steps on single crystal substrates, particularly SiC. The ordered nanometer scale step structures are produced on the top surfaces of mesas by a combination of growth and etching processes. These structures, sometimes referred to herein as artifacts, are to enable step-height calibration, particularly suitable for scanning probe microscopes and profilometers, from less than one nanometer (nm) to greater than 10 nm, with substantially no atomic scale roughness of the plateaus on either side of each step.

Abstract: In a selective growth method, growth interruption is performed at the time of selective growth of a crystal layer on a substrate. Even if the thickness distribution of the crystal layer becomes non-uniform at the time of growth of the crystal layer, the non-uniformity of the thickness distribution of the crystal layer can be corrected by inserting the growth interruption. As a result of growth interruption, an etching rate at a thick portion becomes higher than that at a thin portion, to eliminate the difference in thickness between the thick portion and the thin portion, thereby solving the problem associated with degradation of characteristics due to a variation in thickness of the crystal layer, for example, an active layer. The selective growth method is applied to fabrication of a semiconductor light emitting device including an active layer as a crystal layer formed on a crystal layer having a three-dimensional shape by selective growth.

Abstract: The invention relates to a device and method for depositing one or more layers onto at least one substrate placed inside a reaction chamber. The layers are deposited while using a liquid or solid starting material for one of the reaction gases utilized, which are fed via a gas admission unit to the reaction chamber where they condense or epitaxially grow on the substrate. The gas admission unit comprises a multitude of buffer volumes in which the reaction gasses enter separate of one another, and exit through closely arranged outlet openings while also being spatially separate of one another. The temperature of reaction gases is moderated while passing through the gas admission unit.

Abstract: Semiconductor structure and method of fabricating a semiconductor structure are provided that include a substrate having a first in-plane unstrained lattice constant, a first layer comprising a first semiconductor material on the substrate and having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant and a variable mismatch layer comprising a second semiconductor material disposed between the substrate and the first layer. The variable mismatch layer is configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate. The variable mismatch layer may be a layer having a strained in-plane lattice constant that substantially matches the unstrained lattice constant of the first layer.

Abstract: Carbon nanotubes are implemented in a manner that facilitates their orientation and arrangement for a variety of applications. According to an example embodiment of the present invention, an electric field is used to orient carbon nanotubes along a direction of the electric field (e.g., along a direction generally parallel to an electric field applied between two electrodes). In one implementation, the electric field is used to orient a nanotube that has already been grown. In another implementation, the electric field is used in situ, with nanotubes being aligned while they are grown. With these approaches, carbon nanotubes can be selectively oriented for one or more of a variety of implementations. Furthermore, arrays of aligned carbon nanotubes can be formed extending between circuit nodes having both similar and different orientations.

Abstract: Selected micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates are expected to perform as compliant, thin films for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon, thereby leading to relatively defect-free, heteroepitaxial films of chosen thicknesses. The as-grown epilayers or completed electronic and optoelectronic devices can be bonded to a second substrate such as glass, or plastic following separation thereof from the substrate on which they were formed using preferential etching of a readily detachable, nanoporous silicon or silicon dioxide layer introduced between the generated structures and the substrate.

Abstract: A method of making a Schottky diode comprising the steps of: providing a single crystal diamond comprising a surface; placing the single crystal diamond in a CVD system; heating the diamond to a temperature of at least about 950° C.; providing a gas mixture capable of growing diamond film and comprising a sulfur compound through the CVD system; growing an epitaxial diamond film on the surface of the single crystal diamond; baking the diamond at a temperature of at least about 650° C. in air for a period of time that minimizes oxidation of the diamond; and fabricating a Schottky diode comprising the diamond film. A Schottky diode comprising an epitaxial diamond film and capable of blocking at least about 6 kV in a distance of no more than about 300 &mgr;m.

Abstract: A metal film is deposited on a starting substrate, which is any one of a single crystal sapphire substrate, a substrate comprising a single crystal gallium nitride film grown on a sapphire substrate, and a single crystal semiconductor substrate, and a gallium nitride film is deposited on the metal film to form a laminate substrate. By virtue of the above construction, after the growth of the gallium nitride film, the gallium nitride film can be easily separated from the starting substrate, and a gallium nitride crystal substrate, which has low defect density and has not been significantly contaminated with impurities, can be produced in a simple manner.

Abstract: A method for forming a suspended microstructure is provided. The method includes providing a monocrystalline target substrate and subjecting the surface of the monocrystalline target substrate to ion implantation to form a microstructure layer at the surface of the monocrystalline target substrate. An epitaxial material layer is formed overlying the microstructure layer. A handle substrate is provided and a patterned interposed material layer is provided between the epitaxial material layer and the handle substrate. The epitaxial material layer, the patterned interposed material layer and the handle substrate are affixed. The method further includes thermally treating the monocrystalline target substrate to effect separation between the microstructure layer and a remainder of the monocrystalline target substrate.

Abstract: A method for growing a single crystal GaN film at least 2 microns thick on a Si substrate is disclosed. The method includes growing a prelayer, a buffer layer including AlN on the Si substrate and a plurality of GaN layers and AlN layers deposited alternatively on the top of the AlN buffer layer. By controlling the deposition conditions and timings of the plurality of GaN layers and AlN layers, the single crystal GaN film can be grown thicker than 2 microns without cracks or pits.

Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.

Abstract: MEMS structure and a method of fabricating them from ultrananocrystalline diamond films having average grain sizes of less than about 10 nm and feature resolution of less than about one micron . The MEMS structures are made by contacting carbon dimer species with an oxide substrate forming a carbide layer on the surface onto which ultrananocrystalline diamond having average grain sizes of less than about 10 nm is deposited. Thereafter, microfabrication process are used to form a structure of predetermined shape having a feature resolution of less than about one micron.

Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.

Abstract: A CVD method for growing MgO on a Si(100) substrate coated with a cubic SiC buffer layer provides a single-crystalline MgO film having improved quality.

Abstract: Crystalline pantoprazole sodium Forms II, IV, V, VI, VIII, IX, X, XI, XII, XIII, XIV, XV, XVI, XVII, XVIII, XIX and XX; pantoprazole sodium solvates containing water, acetone, butanol, methylethylketone, dimethylcarbonate, propanol and 2-methylpropanol; and amorphous pantoprazole sodium are disclosed.

Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.

Abstract: A method for making photonic crystal structures using amorphous silicon that is temperature compatible with a wide variety of substrates. Both hydrogenated and non-hydrogenated amorphous silicon may be used.

Abstract: To economically and easily fabricate a single crystal silicon carbide thin film. The apparatus for fabricating a single crystal silicon carbide thin film comprises a film-formation chamber 200 adapted to receive a SOI substrate 100 for film-formation, a gas supply means 300 for supplying various gases G1 to G4 necessary to fabricate a single crystal silicon carbide thin film to the film-formation chamber 200, a gas treatment means 500 for treating argon gas as an inert gas G1, propane gas as a hydrocarbon-based gas G2, hydrogen gas as a carrier gas, and oxygen gas G4 supplied to the film-formation chamber 200, and a temperature control means 400 for controlling the temperature of the film-formation chamber 200.

Abstract: The method of protectively coating metallic uranium which comprises dipping the metallic uranium in a molten alloy comprising about 20-75% of copper and about 80-25% of tin, dipping the coated uranium promptly into molten tin, withdrawing it from the molten tin and removing excess molten metal, thereupon dipping it into a molten metal bath comprising aluminum until it is coated with this metal, then promptly withdrawing it from the bath.