With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/94)
  • Patent number: 8852341
    Abstract: The present invention discloses methods to produce large quantities of polycrystalline GaN for use in the ammonothermal growth of group III-nitride material. High production rates of GaN can be produced in a hydride vapor phase growth system. One drawback to enhanced polycrystalline growth is the increased incorporation of impurities, such as oxygen. A new reactor design using non-oxide material that reduces impurity concentrations is disclosed. Purification of remaining source material after an ammonothermal growth is also disclosed. The methods described produce sufficient quantities of polycrystalline GaN source material for the ammonothermal growth of group III-nitride material.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: October 7, 2014
    Assignee: Sixpoint Materials, Inc.
    Inventors: Edward Letts, Tadao Hashimoto, Masanori Ikari
  • Publication number: 20140295136
    Abstract: A method for manufacturing a single-crystal 4H-SiC substrate includes: preparing a flat 4H-SiC bulk single-crystal substrate; and epitaxially growing a first single-crystal 4H-SiC layer having recesses on the 4H-SiC bulk single-crystal substrate, wherein the first single-crystal 4H-SiC layer has a thickness of X (?m), the recesses have a diameter Y (?m) no smaller than 0.2*X (?m) and no larger than 2*X (?m), and a depth of Z (nm) no smaller than (0.95*X (?m) +0.5 (nm)) and no larger than 10*X (?m).
    Type: Application
    Filed: January 8, 2014
    Publication date: October 2, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Akihito Ohno, Zempei Kawazu, Nobuyuki Tomita, Takanori Tanaka, Yoichiro Mitani, Kenichi Hamano
  • Publication number: 20140290565
    Abstract: The present invention relates to a method for producing graphene on a face-centered cubic metal catalyst having a plane oriented in one direction, and more particularly to a method of producing graphene on a metal catalyst having the (100) or (111) crystal structure and a method of producing graphene using a catalyst metal foil having a single orientation, obtained by electroplating a metal catalyst by a pulse wave current and annealing the metal catalyst. The invention also relates to a method of producing graphene using a metal catalyst, and more particularly to a method of producing graphene, comprising the steps of: alloying a metal catalyst with an alloying element; forming step structures on the metal catalyst substrate in an atmosphere of a gas having a molecular weight of carbon; and supplying hydrocarbon and hydrogen gases to the substrate. On unidirectionally oriented metal catalyst prepared according to the present invention, graphene can be grown uniformly and epitaxially.
    Type: Application
    Filed: October 18, 2012
    Publication date: October 2, 2014
    Inventors: Kang Hyung Kim, Kwan Sub Maeng, Chol Woo Park, Se Won Cha, Se Youn Hong, Byung Hee Hong, Myung Hee Jung, Kyung Eun Kim, Su Beom Park
  • Patent number: 8845992
    Abstract: Affords Group-III nitride single-crystal ingots and III-nitride single-crystal substrates manufactured utilizing the ingots, as well as methods of manufacturing III-nitride single-crystal ingots and methods of manufacturing III-nitride single-crystal substrates, wherein the incidence of cracking during length-extending growth is reduced. Characterized by including a step of etching the edge surface of a base substrate, and a step of epitaxially growing onto the base substrate hexagonal-system III-nitride monocrystal having crystallographic planes on its side surfaces. In order to reduce occurrences of cracking during length-extending growth of the ingot, depositing-out of polycrystal and out-of-plane oriented crystal onto the periphery of the monocrystal must be controlled.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takuji Okahisa, Seiji Nakahata, Tomoki Uemura
  • Publication number: 20140284547
    Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
    Type: Application
    Filed: March 21, 2013
    Publication date: September 25, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20140230723
    Abstract: Provided are: a method for producing a ?-Ga2O3 substrate of which changes in donor concentration in a reducing atmosphere or an inert gas atmosphere are suppressed; and a method for producing a crystal laminate structure that can epitaxially grow a high-quality crystal film having low variability of quality in a reducing atmosphere or an inert gas atmosphere. The method for producing a ?-Ga2O3 substrate includes a step for cutting out a ?-Ga2O3 substrate from a ?-Ga2O3 crystal containing a group IV element; annealing processing in an atmosphere containing a reducing atmosphere and/or an inert gas atmosphere is performed on the ?-Ga2O3 crystal before cutting out the ?-Ga2O3 substrate, or on the cut-out ?-Ga2O3 substrate.
    Type: Application
    Filed: October 12, 2012
    Publication date: August 21, 2014
    Applicant: Tamura Corporation
    Inventors: Takekazu Masui, Yu Yamaoka
  • Publication number: 20140209012
    Abstract: Provided is a base substrate with which a Group-III nitride crystal having a large area and a large thickness can be grown while inhibiting crack generation. A single-crystal substrate for use in growing a Group-III nitride crystal thereon, which satisfies the following expression (1), wherein Z1 (?m) is an amount of warpage of physical shape in a growth surface of the single-crystal substrate and Z2 (?m) is an amount of warpage calculated from a radius of curvature of crystallographic-plane shape in a growth surface of the single-crystal substrate: ?40<Z2/Z1<?1: Expression (1).
    Type: Application
    Filed: March 28, 2014
    Publication date: July 31, 2014
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Kenji FUJITO, Yasuhiro Uchiyama
  • Patent number: 8778774
    Abstract: Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignees: University of Florida Research Foundation, Inc., Texas Instruments Incorporated
    Inventors: Toshikazu Nishida, Antonio Guillermo Acosta, John Anthony Rodriguez, Theodore Sidney Moise
  • Patent number: 8728237
    Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8709923
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8691012
    Abstract: A method of manufacturing zinc oxide nanowires. A metal seed layer is formed on a substrate. The metal seed layer is thermally oxidized to form metal oxide crystals. Zinc oxide nanowires are grown on the metal oxide crystals serving as seeds for growth. The zinc oxide nanowires are aligned in one direction with respect to the surface of the substrate.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Seung Nam Cha, Jae Eun Jang, Byong Gwon Song
  • Patent number: 8652255
    Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
  • Patent number: 8632633
    Abstract: Engineered defects are reproduced in-situ with graphene via a combination of surface manipulation and epitaxial reproduction. A substrate surface that is lattice-matched to graphene is manipulated to create one or more non-planar features in the hexagonal crystal lattice. These non-planar features strain and asymmetrically distort the hexagonal crystal lattice of epitaxially deposited graphene to reproduce “in-situ” engineered defects with the graphene. These defects may be defects in the classic sense such as Stone-Wales defect pairs or blisters, ridges, ribbons and metacrystals. Nano or micron-scale structures such as planar waveguides, resonant cavities or electronic devices may be constructed from linear or closed arrays of these defects. Substrate manipulation and epitaxial reproduction allows for precise control of the number, density, arrangement and type of defects. The graphene may be removed and template reused to replicate the graphene and engineered defects.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: January 21, 2014
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, Brian J. Zelinski, William R. Owens
  • Patent number: 8608849
    Abstract: A method for making zinc oxide nano-structure, the method includes the following steps. Firstly, providing a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, providing a growing substrate and forming a metal layer thereon. Thirdly, depositing a catalyst layer on the metal layer. Fourthly, placing the growing substrate into the reacting room together with a quantity of zinc source material. Fifthly, introducing a oxygen-containing gas into the reacting room. Lastly, heating the reacting room to a temperature range of 500˜1100° C.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: December 17, 2013
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8597427
    Abstract: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoru Okamoto
  • Patent number: 8591652
    Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the material for forming the mask layer consists at least partially of tungsten silicide nitride or tungsten silicide and wherein the semiconductor substrate self-separates from the starting substrate without further process steps.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 26, 2013
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
  • Patent number: 8591856
    Abstract: An electrolytic cell includes a container for holding an electrolyte. A conductively doped single crystal diamond anode electrode is positioned to be disposed within the electrolyte, as is a conductive cathode electrode. Conductors are coupled to the electrodes for coupling to a power supply. An electrolyte inlet and an electrolyte outlet are coupled to the container for causing electrolyte to flow past the electrodes. The anode electrode is downstream from the cathode electrode in one embodiment, such that an electrolyte comprising water is purified by generation of oxygen and/or ozone.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: November 26, 2013
    Assignee: SCIO Diamond Technology Corporation
    Inventors: Patrick J. Doering, Robert C. Linares, Alicia E. Novak, John M. Abrahams, Michael Murray
  • Patent number: 8574528
    Abstract: A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 ?s and about 9.9 ?s.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 5, 2013
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Amitesh Srivastava
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 8530338
    Abstract: A structure consisting of vertically aligned wire arrays on a Si substrate and a method for producing such wire arrays. The wire arrays are fabricated and positioned on a substrate with an orientation and density particularly adapted for conversion of received light to energy. A patterned oxide layer is used to provide for wire arrays that exhibit narrow diameter and length distribution and provide for controlled wire position.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: September 10, 2013
    Assignee: California Institute of Technology
    Inventors: Brendan M. Kayes, Michael A. Filler, Nathan S. Lewis, Harry A. Atwater
  • Patent number: 8529698
    Abstract: Methods, devices, and compositions of matter related to high efficiency InGaN-based photovoltaic devices. The disclosed synthesis of semiconductor heterostructures may be exploited to produce higher efficiency, longer lasting, photovoltaic cells.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: September 10, 2013
    Assignee: Arizona Board Of Regents For And On Behalf Of Arizona State University
    Inventors: Fernando A. Ponce, Rafael Garcia
  • Patent number: 8506707
    Abstract: A compositionally graded material having low defect densities and improved electronic properties is disclosed and described. A compositionally graded inorganic crystalline material can be formed by preparing a crystalline substrate by forming crystallographically oriented pits across an exposed surface of the substrate. A transition region can be deposited on the substrate under substantially epitaxial growth conditions. Single crystal substrates of a wide variety of materials such as diamond, aluminum nitride, silicon carbide, etc. can be formed having relatively low defect rates.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: August 13, 2013
    Inventor: Chien-Min Sung
  • Patent number: 8501143
    Abstract: A single crystal diamond prepared by CVD and having one or more electronic characteristics; making the diamond suitable for electronic applications. Also provided is a method of making the single crystal CVD diamond.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: August 6, 2013
    Assignee: Element Six Ltd.
    Inventors: Geoffrey Alan Scarsbrook, Philip Maurice Martineau, John Lloyd Collins, Ricardo Simon Sussmann, Bärbel Susanne Charlotte Dorn, Andrew John Whitehead, Daniel James Twitchen
  • Publication number: 20130160699
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Application
    Filed: February 8, 2013
    Publication date: June 27, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8460464
    Abstract: A method for producing one or more single crystalline diamonds. The method comprises placing one or more substrates on a substrate holder in chemical vapor vaporization (CVD) chamber. A mixture of gases including at least one gas having a carbon component is provided adjacent to the one or more substrates in the CVD chamber. Thereafter, the mixture of gases is exposed to microwave radiation to generate a plasma. Reactive species of nitrogen produced in a remote reactive gas generator are introduced in the plasma. Then, the one or more substrates are exposed to the plasma, such that diamond growth occurs at a rate of 10 to 100 microns per hour, to produce one or more single crystalline diamonds.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: June 11, 2013
    Inventor: Rajneesh Bhandari
  • Publication number: 20130095305
    Abstract: Provided are a graphene pattern and a process of preparing the same. Graphene is patterned in a predetermined shape on a substrate to form the graphene pattern. The graphene pattern can be formed by forming a graphitizing catalyst pattern on a substrate, contacting a carbonaceous material with the graphitizing catalyst and heat-treating the resultant.
    Type: Application
    Filed: November 20, 2012
    Publication date: April 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Patent number: 8404042
    Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8404045
    Abstract: An underlying film 2 of a group III nitride is formed on a substrate 1 by vapor phase deposition. The substrate 1 and the underlying film 2 are subjected to heat treatment in the present of hydrogen to remove the underlying film 2 so that the surface of the substrate 1 is roughened. A seed crystal film 4 of a group III nitride single crystal is formed on a surface of a substrate 1A by vapor phase deposition. A group III nitride single crystal 5 is grown on the seed crystal film 4 by flux method.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: March 26, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshitaka Kuraoka, Shigeaki Sumiya, Makoto Miyoshi, Minoru Imaeda
  • Patent number: 8404571
    Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Tatsuya Tanabe
  • Patent number: 8394197
    Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 12, 2013
    Assignee: Sub-One Technology, Inc.
    Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
  • Publication number: 20130059124
    Abstract: An R-cut substrate is prepared by cutting lumbered synthetic quartz crystal along a surface parallel to the R-face. The surface of the thus obtained R-cut substrate has a structure in which the R-face smoothest in terms of the crystal structure accounts for the most part of the surface, and the m- and r-faces are exposed on this surface to extend in a direction parallel to the X-axis albeit only slightly upon processing. After catalytic metals are arranged on the surface of the R-cut substrate, a carbon source gas is supplied onto the surface of the R-cut substrate to grow carbon nanotubes in accordance with the crystal lattice structure using the crystal metals as nuclei. This makes it possible to manufacture carbon nanotubes with a good orientation and linearity.
    Type: Application
    Filed: March 1, 2011
    Publication date: March 7, 2013
    Inventors: Shigeo Maruyama, Shohei Chiashi, Hiroto Okabe, Masami Terasawa, Shuichi Kono, Tadashi Sato
  • Patent number: 8349076
    Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 8, 2013
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: In-Jae Song, Jai-yong Han
  • Patent number: 8328935
    Abstract: The present invention is a method of manufacturing polycrystalline silicon rods, wherein silicon is deposited onto a silicon core wire by a chemical vapor deposition (CVD) method such that a silicon member, which is cut out from a single-crystalline silicon ingot at an off-angle range of 5 to 40 degrees relative to a crystal habit line of the ingot, is used as the silicon core wire. The single-crystalline silicon ingot is preferably grown by a Czochralski (CZ) method or floating zone (FZ) method, such that the ingot preferably has an interstitial oxygen concentration of 7 ppma to 20 ppma. Silicon rods produced by this method are less likely to suffer a breakage caused by cleavage during the growth process of polycrystalline silicon during CVD, and exhibit improved FZ method success rates. The polycrystalline silicon rods produced by this method also have low impurity contamination and high single-crystallization efficiency.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: December 11, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Michihiro Mizuno, Shinichi Kurotani, Shigeyoshi Netsu, Kyoji Oguro
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Publication number: 20120305983
    Abstract: The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Kenji Fujito, Kazumasa Kiyomi
  • Publication number: 20120304918
    Abstract: A method of growing a p-type thin film of ?-Ga2O3 includes preparing a substrate including a ?-Ga2O3 single crystal, and growing a p-type thin film of ?-Ga2O3 on the substrate. The p-type thin film is grown in a manner that Ga in the thin film is replaced by a p-type dopant selected from H, Li, Na, K, Rb, Cs, Fr, Be, Mg, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, and Pb.
    Type: Application
    Filed: August 13, 2012
    Publication date: December 6, 2012
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Patent number: 8323402
    Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
  • Publication number: 20120269717
    Abstract: The present application relates generally to methods for growth of high quality graphene films. In particular, a method is provided for forming a graphene film using a modified chemical vapor deposition process using an oxygen-containing hydrocarbon liquid precursor. Desirably, the graphene films are a single-layer and have a single grain continuity of at least 1 ?m2.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: THE AEROSPACE CORPORATION
    Inventors: Gouri Radhakrishnan, Paul Michael Adams
  • Patent number: 8273177
    Abstract: An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8268076
    Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
  • Patent number: 8258051
    Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
    Type: Grant
    Filed: May 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8246746
    Abstract: The present invention is directed to new laser-related uses for single-crystal diamonds produced by chemical vapor deposition. One such use is as a heat sink for a laser; another such use is as a frequency converter. The invention is also directed to a ?(3) nonlinear crystalline material for Raman laser converters comprising single crystal diamond.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 21, 2012
    Assignee: Carnegie Institution of Washington
    Inventors: Russell J. Hemley, Ho-Kwang Mao, Chih-Shiue Yan
  • Patent number: 8226767
    Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: July 24, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
  • Patent number: 8221548
    Abstract: A process for producing a diamond thin-film includes forming a diamond crystal thin-film on a substrate and firing the diamond crystal thin-film at a sufficient temperature under high pressure under which a diamond is stable. A diamond single-crystal substrate having a diamond single-crystal thin-film formed thereon is placed in an ultra-high-pressure and high-temperature firing furnace to anneal the diamond single-crystal thin-film under the conditions of 1200° C. and 6 GPa.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 17, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8216367
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 10, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8197598
    Abstract: A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600˜1200° C.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: June 12, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8198628
    Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: June 12, 2012
    Assignee: Soitec
    Inventors: Robert Langer, Hacène Lahreche
  • Patent number: 8187379
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20120118222
    Abstract: A method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in its main surface is more than 1.0 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a main surface side of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate, the single crystal film in the composite substrate being an SiC film. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage is provided.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 17, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke FUJIWARA, Koji Uematsu, Yoshiyuki Yamamoto, Issei Satoh
  • Publication number: 20120112320
    Abstract: A production process for a nitride semiconductor crystal, comprising growing a semiconductor layer on a seed substrate to obtain a nitride semiconductor crystal, wherein the seed substrate comprises a plurality of seed substrates made of the same material, at least one of the plurality of seed substrates differs in the off-angle from the other seed substrates, and a single semiconductor layer is grown by disposing the plurality of seed substrates in a semiconductor crystal production apparatus, such that when the single semiconductor layer is grown on the plurality of seed substrates, the off-angle distribution in the single semiconductor layer becomes smaller than the off-angle distribution in the plurality of seed substrates.
    Type: Application
    Filed: December 1, 2011
    Publication date: May 10, 2012
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Shuichi KUBO, Kenji Shimoyama, Kazumasa Kiyomi, Kenji Fujito, Yutaka Mikawa