With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/94)
  • Patent number: 7771532
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: August 10, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Patent number: 7687798
    Abstract: The present invention relates a method for epitaxial growth of a second group III-V crystal having a second lattice constant over a first group III-V crystal having a first lattice constant, wherein strain relaxation associated with lattice-mismatched epitaxy is suppressed and thus dislocation defects do not form. In the first step, the surface of the first group III-V crystal (substrate) is cleansed by desorption of surface oxides. In the second step, a layer of condensed group-V species is condensed on the surface of the first group III-V crystal. In the third step, a mono-layer of constituent group-III atoms is deposited over the layer of condensed group-V species in order for the layer of constituent group-III atoms to retain the condensed group-V layer. Subsequently, the mono-layer of group-III atoms is annealed at a higher temperature.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 30, 2010
    Assignee: HRL Laboratories, LLC
    Inventor: Binqiang Shi
  • Patent number: 7686885
    Abstract: In some embodiments, the present invention addresses the challenges of fabricating nanorod arrays comprising a heterogeneous composition and/or arrangement of the nanorods. In some embodiments, the present invention is directed to multicomponent nanorod arrays comprising nanorods of at least two different chemical compositions, and to methods of making same. In some or other embodiments, the nanorods are spatially positioned within the array in a pre-defined manner.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: March 30, 2010
    Assignee: General Electric Company
    Inventors: Anthony Yu-Chung Ku, Reed Roeder Corderman, Krzysztof Slowinski
  • Patent number: 7686886
    Abstract: A method for forming a structure of a desired cross-section on a substrate is provided. The method provides a seed structure comprising at least one support layer on the substrate. The support layer has a geometric shape related to the desired cross-section of the structure and is diffusive to a precursor constituent. The method further includes growing the structure by supplying at least one precursor constituent on the substrate. The desired cross-section of the structure is defined by the geometric shape of at least one support layer.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Walter H Riess, Heike E Riel, Siegfried F Karg, Heinz Schmid
  • Patent number: 7678194
    Abstract: A method and apparatus for generating gas for a processing system is provided. In one embodiment, an apparatus for generating gas for a processing system includes a canister having at least one baffle disposed between two ports and containing a precursor material. The precursor material is adapted to produce a gas vapor when heated to a defined temperature at a defined pressure. The baffle forces a carrier gas to travel an extended mean path between the inlet and outlet ports. In another embodiment, an apparatus for generating gas includes a canister having a tube that directs a carrier gas flowing into the canister away from a precursor material disposed within the canister.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: March 16, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Ling Chen, Vincent W. Ku
  • Patent number: 7678195
    Abstract: A method of growing bulk single crystals of an AlN on a single crystal seed is provided, wherein an AlN source material is placed within a crucible chamber in spacial relationship to a seed fused to the cap of the crucible. The crucible is heated in a manner sufficient to establish a temperature gradient between the source material and the seed with the seed at a higher temperature than the source material such that the outer layer of the seed is evaporated, thereby cleaning the seed of contaminants and removing any damage to the seed incurred during seed preparation. Thereafter, the temperature gradient between the source material and the seed is inverted so that the source material is sublimed and deposited on the seed, thereby growing a bulk single crystal of AlN.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: March 16, 2010
    Assignee: North Carolina State University
    Inventors: Raoul Schlesser, Vladimir Noveski, Zlatko Sitar
  • Patent number: 7651927
    Abstract: A semiconductor device includes a substrate and a semiconductor layer formed on the substrate. The substrate has: a flat region provided in a main surface thereof; a first indentation region provided in a portion of the main surface different from the flat region and formed with first recesses; and a second indentation region provided between the first indentation region and the flat region, formed with second recesses, and having a lower probability of occurrence of growth nuclei than the first indentation region and a higher probability than the flat region in the case where a crystal of a semiconductor is grown on the main surface.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: January 26, 2010
    Assignee: Panasonic Corporation
    Inventor: Yuji Takase
  • Publication number: 20100012021
    Abstract: A precursor chiral nanotube with a specified chirality is grown using an epitaxial process and then cloned. A substrate is provided of crystal material having sheet lattice properties complementary to the lattice properties of the selected material for the nanotube. A cylindrical surface(s) having a diameter of 1 to 100 nanometers are formed as a void in the substrate or as crystal material projecting from the substrate with an orientation with respect to the axes of the crystal substrate corresponding to the selected chirality. A monocrystalline film of the selected material is epitaxially grown on the cylindrical surface that takes on the sheet lattice properties and orientation of the crystal substrate to form a precursor chiral nanotube. A catalytic particle is placed on the precursor chiral nanotube and atoms of the selected material are dissolved into the catalytic particle to clone a chiral nanotube from the precursor chiral nanotube.
    Type: Application
    Filed: July 16, 2008
    Publication date: January 21, 2010
    Inventors: DELMAR L. BARKER, William R. Owens
  • Patent number: 7628856
    Abstract: There is disclosed a method for producing a substrate for single crystal diamond growth, comprising at least a step of preliminarily subjecting a substrate before single crystal diamond growth to a bias treatment for forming a diamond nucleus thereon by a direct-current discharge in which an electrode in a substrate side is a cathode, and wherein in the treatment, at least, a temperature of the substrate from 40 sec after an initiation of the bias treatment to an end of the bias treatment is held in a range of 800° C.±60° C. There can be provided a method for producing a substrate for single crystal diamond growth, by which a single crystal diamond can be grown more certainly.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: December 8, 2009
    Assignees: Shin-Etsu Chemical Co., Ltd., AGD Material Co.
    Inventors: Atsuhito Sawabe, Hitoshi Noguchi, Shintaro Maeda
  • Patent number: 7628855
    Abstract: Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: December 8, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Neal R. Rueger
  • Patent number: 7625448
    Abstract: The invention relates to a device for depositing especially crystalline layers on at least one especially crystalline substrate in a process chamber comprising a top and a vertically opposing heated bottom for receiving the substrates. A gas-admittance body forming vertically superimposed gas-admittance regions is used to separately introduce at least one first and one second gaseous starting material, said starting materials flowing through the process chamber with a carrier gas in the horizontal direction. The gas flow homogenises in an admittance region directly adjacent to the gas-admittance body, and the starting materials are at least partially decomposed, forming decomposition products which are deposited on the substrates in a growth region adjacent to the admittance region, under continuous depletion of the gas flow. An additional gas-admittance region of the gas-admittance body is essential for one of the two starting materials, in order to reduce the horizontal extension of the admittance region.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: December 1, 2009
    Assignee: Aixtron AG
    Inventors: Martin Dauelsberg, Martin Conor, Gerhard Karl Strauch, Johannes Kaeppeler
  • Patent number: 7625447
    Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10?6 to 10?8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 1, 2009
    Assignee: Japan Science and Technology Agency
    Inventors: Jun Suda, Hiroyuki Matsunami, Norio Onojima
  • Patent number: 7621998
    Abstract: The present invention relates to a freestanding, thick, single crystalline gallium nitride (GaN) film having significantly reduced bending deformation. The inventive GaN film having a crystal tilt angle of C-axis to the <0001> direction per surface distance of 0.0022°/mm exhibits little bending deformation even at a thickness of 1 mm or more, and therefore, is beneficially used as a substrate for a luminescent device.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: November 24, 2009
    Assignee: Samsung Corning Co., Ltd.
    Inventors: Changho Lee, Hyun Min Shin, Sun-Hwan Kong, Hae Yong Lee
  • Patent number: 7621999
    Abstract: An epitaxial growing method in which a crystal of AlxGa1-xN wherein x is a desirable constituent ratio can be grown on an Si substrate or sapphire substrate according to the HVPE process. Crystal of AlxGa1-xN is grown according to the HVPE process in which use is made of an aluminum material, a gallium material, an ammonia material and a carrier gas. The carrier gas consists of an inert gas and hydrogen, and the partial pressure of hydrogen is set so as to range from 0 to <0.1. As a result, the relationship between feeding ratio among materials and constituent ratio of grown crystal can be made linear, thereby enhancing the controllability of crystal composition.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: November 24, 2009
    Assignee: Tokyo University of Agriculture and Technology TLO Co., Ltd
    Inventors: Akinori Koukitu, Yoshinao Kumagai
  • Patent number: 7618492
    Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Laura Pescini, Achim Gratz, Veronika Polei
  • Patent number: 7615116
    Abstract: In a vapor phase growth apparatus including a reaction chamber, a susceptor, a lift pin, an upper heating device, and a lower heating device, a heating ratio between the upper heating ratio and the lower heating ratio is adjusted.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 10, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koichi Kanaya, Tsuyoshi Nishizawa
  • Patent number: 7615203
    Abstract: A single crystal diamond grown by vapor phase synthesis, wherein when one main surface is irradiated with a linearly polarized light considered to be the synthesis of two mutually perpendicular linearly polarized light beams, the phase difference between the two mutually perpendicular linearly polarized light beams exiting another main surface on the opposite side is, at a maximum, not more than 50 nm per 100 ?m of crystal thickness over the entire crystal. This single crystal diamond is of a large size and high quality unattainable up to now, and has characteristics that are extremely desirable in semiconductor device substrates and are applied to optical components of which low strain is required.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: November 10, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Yamamoto, Kiichi Meguro, Takahiro Imai
  • Publication number: 20090256162
    Abstract: A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defects to a temperature that thermodynamically increases the number of point defects and resulting states in the crystal, and then cooling the heated crystal at a sufficiently rapid rate to maintain an increased concentration of point defects in the cooled crystal.
    Type: Application
    Filed: June 24, 2009
    Publication date: October 15, 2009
    Applicant: CREE, INC.
    Inventors: Jason Ronald Jenny, David Phillip Malta, Hudson McDonald Hobgood, Stephan Mueller, Valeri F. Tsvetkov
  • Patent number: 7597757
    Abstract: A ZnO film with a C-axis preference is provided with a corresponding fabrication method. The method includes: forming a substrate; forming an amorphous Al2O3 film overlying the substrate; and, forming a ZnO film overlying the Al2O3 film at a substrate temperature of about 170° C., having a C-axis preference responsive to the adjacent Al2O3 film. The substrate can be a material such as Silicon (Si) (100), Si (111), Si (110), quartz, glass, plastic, or zirconia. The Al2O3 film can be deposited using a chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering process. Typically, the Al2O3 layer has a thickness in the range of about 3 to 15 nanometers (nm). The step of forming the ZnO film having a C-axis preference typically means that the ZnO film has a (002) peak at least 5 times greater than the (100) peak, as measured by X-ray diffraction (XRD).
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: October 6, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: John F. Conley, Jr., Yoshi Ono
  • Patent number: 7594967
    Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: September 29, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
  • Publication number: 20090239097
    Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Applicant: International Business Machines Corporation
    Inventors: Jack Oon Chu, Deborah Ann Neumayer
  • Publication number: 20090235862
    Abstract: A method of manufacturing zinc oxide nanowires. A metal seed layer is formed on a substrate. The metal seed layer is thermally oxidized to form metal oxide crystals. Zinc oxide nanowires are grown on the metal oxide crystals serving as seeds for growth. The zinc oxide nanowires are aligned in one direction with respect to the surface of the substrate.
    Type: Application
    Filed: September 24, 2008
    Publication date: September 24, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Nam CHA, Jae Eun JANG, Byong Gwon SONG
  • Patent number: 7579222
    Abstract: Method of manufacturing a thin film device substrate wherein no trench fabrication is required to be applied onto the substrate surface, and a material which is impervious to light can be used, and the substrate can be peeled off quickly. Firstly, a peeling-off film, a silicon oxide film and an amorphous silicon film are formed in succession on a glass substrate, and the amorphous silicon film is irradiated from above to obtain a polycrystalline silicon film. Subsequently, using the polycrystalline silicon film as an active layer, a TFT is formed, and then a plastic substrate is bonded thereon, and finally the glass substrate is peeled off with the peeling-off film, to complete transfer of the TFT. Because the peeling-off film has a gap space, its etching rate is high. Therefore, it is unnecessary to form a trench for supplying an etchant on the surface of the glass substrate.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: August 25, 2009
    Assignee: NEC Corporation
    Inventors: Mitsuru Nakata, Kazushige Takechi, Hiroshi Kanoh
  • Patent number: 7576372
    Abstract: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN layer to make the free-standing, single crystal AlGaN wafer. Forming the single crystal AlGaN layer may comprise depositing AlGaN by vapor phase epitaxy (VPE) using aluminum and gallium halide reactant gases and a nitrogen-containing reactant gas. The growth of the AlGaN layer using VPE provides commercially acceptable rapid growth rates. In addition, the AlGaN layer can be devoid of carbon throughout. Because the AlGaN layer produced is high quality single crystal, it may have a defect density of less than about 107cm?2.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 18, 2009
    Assignee: Crystal Photonics, Incorporated
    Inventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou, David W. Hill
  • Patent number: 7572331
    Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: August 11, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Konstantin Bourdelle, Ian Cayrefourcq, Mark Kennard
  • Patent number: 7566364
    Abstract: Provided may be a method of fabricating nanowires and a method of fabricating a transistor having the same. The method may include: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed in the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface; supplying gaseous crystal growth materials through the second apertures; and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer. The nanowires may be made of crystalline materials, e.g., Si or SiGe, and may be formed parallel to the substrate.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: July 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wenxu Xianyu, Young-Soo Park, Takashi Noguchi, Hans S. Cho, Xiaoxin Zhang, Huaxiang Yin
  • Patent number: 7560086
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: July 14, 2009
    Assignee: Apollo Diamond, Inc.
    Inventors: Robert C. Linares, Patrick J Doering
  • Patent number: 7556687
    Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: July 7, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Publication number: 20090151623
    Abstract: A method and system for forming high-quality epitaxial films. In one embodiment, the method includes cleaning a substrate, reducing adsorbed moisture on the substrate in a predefined temperature and predefined oxygen level atmosphere, and removing native oxide from the substrate. The method also includes prebaking the substrate and growing an epitaxial layer doped with an impurity, wherein the impurity has a nano-impurity profile.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: ATMEL CORPORATION
    Inventor: Darwin Gene Enicks
  • Patent number: 7540920
    Abstract: Embodiments of the invention generally provide a composition of silicon compounds and methods for using the silicon compounds to deposit a silicon-containing film. The processes employ introducing the silicon compound to a substrate surface and depositing a portion of the silicon compound, the silicon motif, as the silicon-containing film. The ligands are another portion of the silicon compound and are liberated as an in-situ etchant. The in-situ etchants supports the growth of selective silicon epitaxy. Silicon compounds include SiRX6, Si2RX6, Si2RX8, wherein X is independently hydrogen or halogen and R is carbon, silicon or germanium. Silicon compound also include compounds comprising three silicon atoms, fourth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen, as well as, comprising four silicon atoms, fifth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: June 2, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Paul B. Comita, Lance A. Scudder, David K. Carlson
  • Patent number: 7537660
    Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: May 26, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Patent number: 7534310
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: May 19, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
  • Patent number: 7524376
    Abstract: A crystal growth setup within a physical vapor transport growth furnace system for producing AlN monocrystal boules at high temperatures includes a crucible effective to contain an AlN source material and a growing AlN crystal boule. This crucible has a thin wall thickness in at least that portion housing the growing AlN crystal boule. Other components include a susceptor, in case of an inductive heating, or a heater, in case of a resistive heating, a thermal insulation enclosing the susceptor or heater effective to provide a thermal gradient inside the crucible in the range of 5-100° C./cm and a furnace chamber capable of being operated from a vacuum (<0.1 torr) to a gas pressure of at least 4000 torr through filling or flowing a nitrogen gas or a mixture of nitrogen gas and argon gas. The high temperatures contribute to a high boule growth rate and the thin wall thickness contributes to reduced imparted stress during boule removal.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 28, 2009
    Assignee: Fairfield Crystal Technology, LLC
    Inventor: Shaoping Wang
  • Patent number: 7524372
    Abstract: A method for manufacturing a diamond single crystal substrate, in which a single crystal is grown from a diamond single crystal serving as a seed substrate by vapor phase synthesis, said method comprising: preparing a diamond single crystal seed substrate which has a main surface whose planar orientation falls within an inclination range of not more than 8 degrees relative to a {100} plane or a {111} plane, as a seed substrate; forming a plurality of planes of different orientation which are inclined in the outer peripheral direction of the main surface relative to the main surface on one side of this seed substrate, by machining; and then growing a diamond single crystal by vapor phase synthesis.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 28, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
  • Patent number: 7507293
    Abstract: Fabrication of a photonic crystal is described. A patterned array of nanowires is formed, the nanowires extending outward from a surface, the nanowires comprising a catalytically grown nanowire material. Spaces between the nanowires are filled with a slab material, the patterned array of nanowires defining a patterned array of channels in the slab material. The nanowire material is then removed from the channels.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: March 24, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhiyong Li, R. Stanley Williams, M. Saif Islam, Philip J. Kuekes
  • Patent number: 7501023
    Abstract: A method and apparatus for growing low defect, optically transparent, colorless, crack-free, substantially flat, single crystal Group III nitride epitaxial layers with a thickness of at least 10 microns is provided. These layers can be grown on large area substrates comprised of Si, SiC, sapphire, GaN, AlN, GaAs, AlGaN and others. In one aspect, the crack-free Group III nitride layers are grown using a modified HVPE technique. If desired, the shape and the stress of Group III nitride layers can be controlled, thus allowing concave, convex and flat layers to be controllably grown. After the growth of the Group III nitride layer is complete, the substrate can be removed and the freestanding Group III nitride layer used as a seed for the growth of a boule of Group III nitride material. The boule can be sliced into individual wafers for use in the fabrication of a variety of semiconductor structures (e.g., HEMTs, LEDs, etc.).
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: March 10, 2009
    Assignee: Technologies and Devices, International, Inc.
    Inventors: Vladimir A. Dmitriev, Yuri V. Melnik
  • Patent number: 7501022
    Abstract: Methods for producing silicon carbide crystals, seed crystal holders and seed crystal for use in producing silicon carbide crystals and silicon carbide crystals are provided. Silicon carbide crystals are produced by forcing nucleation sites of a silicon carbide seed crystal to a predefined pattern and growing silicon carbide utilizing physical vapor transport (PVT) so as to provide selective preferential growth of silicon carbide corresponding to the predefined pattern. Seed holders and seed crystals are provided for such methods. Silicon carbide crystals having regions of higher and lower defect density are also provided.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 10, 2009
    Assignee: Cree, Inc.
    Inventor: Stephan Mueller
  • Patent number: 7491269
    Abstract: The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: February 17, 2009
    Assignee: Thales
    Inventors: Pierre Legagneux, Didier Pribat, Yannig Nedellec
  • Patent number: 7488385
    Abstract: The invention concerns the preparation of gallium nitride films by epitaxy with reduced defect density levels. It concerns a method for producing a gallium nitride (GaN) film by epitaxial deposition of GaN. The invention is characterized in that it comprises at least a step of epitaxial lateral overgrowth and in that it comprises a step which consists in separating part of the GaN layer from its substrate by embrittlement through direct ion implantation in the GaN substrate. The invention also concerns the films obtainable by said method as well as the optoelectronic and electronic components provided with said gallium nitride films.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: February 10, 2009
    Assignee: Lumilog
    Inventors: Hacène Lahreche, Gilles Nataf, Bernard Beaumont
  • Patent number: 7481880
    Abstract: A method of crystallizing amorphous silicon includes forming an amorphous silicon layer on a substrate, placing a mask over the substrate including the amorphous silicon layer, and applying a laser beam onto the amorphous silicon layer through the mask to form a first crystallized region, the laser beam having an energy intensity high enough to completely melt the amorphous silicon layer, wherein the mask comprises a base substrate, a phase shift layer on the base substrate, having a plurality of first stripes having a first width separated by slits, and a blocking layer overlapping the phase shift layer, having a plurality of second stripes having a second width narrower than the first width, the second stripes being parallel to the first stripes.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: January 27, 2009
    Assignee: LG Display Co., Ltd.
    Inventor: Kwang-Jo Hwang
  • Patent number: 7473315
    Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: January 6, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
  • Patent number: 7465354
    Abstract: A process, for patterning a thin film that is highly resistant to conventional etching processes and that is to be deposited at a high substrate temperature, is disclosed. The process uses a liftoff method wherein a refractory material has been substituted for the conventional organic resin. The method is particularly useful for the fabrication of tunable microwave devices and ferroelectric memory elements.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: December 16, 2008
    Assignee: National University of Singapore
    Inventors: Chong Kim Ong, Chin Yaw Tan
  • Publication number: 20080303118
    Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 11, 2008
    Inventors: Chantal Arena, Fabrice Letertre
  • Patent number: 7462239
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 9, 2008
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Patent number: 7459024
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: December 2, 2008
    Assignee: Apollo Diamond, Inc.
    Inventors: Robert C. Linares, Patrick J. Doering
  • Patent number: 7459025
    Abstract: Systems and methods for transferring a thin film from a substrate onto another substrate, a layer of the same area as the substrate, of a thickness from sub-micron to tens of micron, and of the thickness and flatness required by VLSI and MEMS applications, and with sufficiently low defect density in the transferred layer are disclosed. The method enables separating a solid layer from a supply substrate and optionally transferring the solid layer onto a target substrate. The method generally includes providing the solid layer on a hydrogen recombination region containing hydrogen-recombination-dopant at a concentration higher than that of the solid layer. The supply substrate includes the solid layer, a mother substrate, and the hydrogen recombination region. The hydrogen recombination region may form a part of the mother substrate or may be separate therefrom.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: December 2, 2008
    Inventor: Tien-Hsi Lee
  • Patent number: 7455729
    Abstract: The invention concerns a method for preparing gallium nitride films by vapour-phase epitaxy with low defect densities. The invention concerns a method for producing a gallium nitride (GaN) film from a substrate by vapour-phase epitaxy deposition of gallium nitride. The invention is characterized in that the gallium nitride deposition comprises at least one step of vapour-phase epitaxial lateral overgrowth, in that at least one of said epitaxial lateral overgrowth steps is preceded by etching openings either in a dielectric mask previously deposited, or directly into the substrate, and in that it consists in introducing a dissymmetry in the environment of dislocations during one of the epitaxial lateral overgrowth steps so as to produce a maximum number of curves in the dislocations, the curved dislocations not emerging at the surface of the resulting gallium nitride layer. The invention also concerns the optoelectronic and electronic components produced from said gallium nitride films.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: November 25, 2008
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Pierre Faurie
  • Patent number: 7445673
    Abstract: Gallium nitride substrates are grown by epitaxial lateral overgrowth using multiple steps. On a masked substrate having openings areas, selective growth produces first triangular stripes in which most of the threading dislocations are bent at 90°. In a second step, growth conditions are changed to increase the lateral growth rate and produce a flat (0001) surface. At this stage the density of dislocations on the surface is <5×107 cm 2. Dislocations are primarily located at the coalescence region between two laterally grown facets pinching off together. To further decrease the dislocation density a second masking step is achieved, with the openings exactly located above the first ones. Threading dislocations (TDs) of the coalescence region do not propagate in the top layer. Therefore the density of dislocations is lowered below <1×107 cm lover the entire surface.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: November 4, 2008
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart
  • Patent number: 7442252
    Abstract: The present invention provides methods for producing a multi-element oxide single crystal which contains Bi, which has high crystallinity independently of a preparation process, and which is represented by the formula (Bi2O2)Am?1BmO3m+1, wherein A is Sr, Ba, Ca, or Bi and B is Ti, Ta, or Nb. A flux layer, containing a composition satisfying the inequality 0<CuO/Bi2O3<2 and/or 0?TiO/Bi2O3<7/6 on a molar basis is deposited on a wafer and a single-crystalline thin-film is then deposited on the flux layer placed on the wafer. A melt of a composition which contains raw materials and a flux and which satisfies the above inequality is prepared and the melt is cooled such that a single crystal is grown. A CuO flux layer is deposited on a wafer and Bi—Ti—O is supplied to the flux layer using a Bi6Ti3O12, Bi7Ti3O12, or Bi8Ti3O12 target of which the Bi content is greater than that of an object film such that a Bi4Ti3O12 single-crystalline thin-film is formed above the wafer.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 28, 2008
    Assignee: Japan Science and Technology Agency
    Inventors: Hideomi Koinuma, Yuji Matsumoto, Ryota Takahashi
  • Patent number: 7438762
    Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: October 21, 2008
    Assignee: Stanley Electric Co., Ltd., Tokyo Denpa Co., Ltd., and Tohoku University
    Inventors: Hiroyuki Kato, Michihiro Sano, Katsumi Maeda, Hiroshi Yoneyama, Takafumi Yao, Meoung Whan Cho