Coating (e.g., Masking, Implanting) Patents (Class 117/95)
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Publication number: 20090176114Abstract: The present invention provides a base substrate for epitaxial diamond film capable of epitaxially growing a large area of high quality diamond, having a diameter of 1 inch (2.5 cm) or more, on an iridium base by using the CVD method, a method for producing the base substrate for epitaxial diamond film, an epitaxial diamond film produced with the base substrate for epitaxial diamond film and a method for producing the epitaxial diamond film. An iridium (Ir) film is formed by epitaxial growth on a single crystal magnesium oxide (MgO) substrate or a single crystal sapphire (?-Al2O3) substrate by means of a vacuum deposition method or a sputtering method, and a bias nucleus generation process of forming epitaxial diamond nuclei is applied to the surface of the iridium (Ir) base formed as a film by exposing an ion-containing direct current plasma to the surface of the iridium (Ir) base formed as a film.Type: ApplicationFiled: February 5, 2007Publication date: July 9, 2009Inventors: Atsuhito Sawabe, Shintaro Maeda
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Patent number: 7556687Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).Type: GrantFiled: November 22, 2006Date of Patent: July 7, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka Sato, Seiji Nakahata
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Patent number: 7553370Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.Type: GrantFiled: December 19, 2005Date of Patent: June 30, 2009Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
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Patent number: 7547359Abstract: An aerosol of a powder composed of helium carrier gas and particles of a hexagonal aluminum nitride is charged through a transfer pipe 3 into a film deposition chamber 4 whose interior is depressurized by gas evacuation using a vacuum pump 5 to maintain a degree of vacuum of 200-8000 Pa during supply of the carrier gas and the aerosol is blown from a nozzle 6 provided on the end of the transfer pipe 3 inside the film deposition chamber 4 to impinge on a substrate fastened to a substrate holder 7 to make the impact force of the particles at collision with the substrate 4 GPa or greater, thereby transforming the crystal structure of the aluminum nitride from hexagonal to cubic to deposit cubic aluminum nitride on the substrate.Type: GrantFiled: March 19, 2004Date of Patent: June 16, 2009Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Atsushi Iwata, Jun Akedo
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Patent number: 7540920Abstract: Embodiments of the invention generally provide a composition of silicon compounds and methods for using the silicon compounds to deposit a silicon-containing film. The processes employ introducing the silicon compound to a substrate surface and depositing a portion of the silicon compound, the silicon motif, as the silicon-containing film. The ligands are another portion of the silicon compound and are liberated as an in-situ etchant. The in-situ etchants supports the growth of selective silicon epitaxy. Silicon compounds include SiRX6, Si2RX6, Si2RX8, wherein X is independently hydrogen or halogen and R is carbon, silicon or germanium. Silicon compound also include compounds comprising three silicon atoms, fourth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen, as well as, comprising four silicon atoms, fifth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen.Type: GrantFiled: October 17, 2003Date of Patent: June 2, 2009Assignee: Applied Materials, Inc.Inventors: Kaushal K. Singh, Paul B. Comita, Lance A. Scudder, David K. Carlson
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Patent number: 7540919Abstract: A process for making silicon ingots using a multi-part, reusable, graphite crucible of at least two mold pieces configured for assembly into an open top mold having an interior surface functional as a mold cavity for receiving molten silicon; removing or reducing a prior applied release coating from the interior surface until a uniformly smooth finish is achieved; coating the interior surface with a first layer of release coating comprising silicon nitride; coating the interior surface with a second layer of release coat comprising silica suspended in water; coating the interior surface with a third layer of release coat comprising silicon nitride; curing the release coat on said crucible; casting a silicon ingot in the crucible; and then repeating the prior steps multiple times.Type: GrantFiled: March 31, 2006Date of Patent: June 2, 2009Assignee: GT Solar IncorporatedInventors: Santhana Raghavan Parthasarathy, Yuepeng Wan, Carl Chartier, Jonathan A Talbott, Kedar P Gupta
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Patent number: 7537660Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.Type: GrantFiled: May 30, 2006Date of Patent: May 26, 2009Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
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Patent number: 7534310Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: May 17, 2006Date of Patent: May 19, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7524372Abstract: A method for manufacturing a diamond single crystal substrate, in which a single crystal is grown from a diamond single crystal serving as a seed substrate by vapor phase synthesis, said method comprising: preparing a diamond single crystal seed substrate which has a main surface whose planar orientation falls within an inclination range of not more than 8 degrees relative to a {100} plane or a {111} plane, as a seed substrate; forming a plurality of planes of different orientation which are inclined in the outer peripheral direction of the main surface relative to the main surface on one side of this seed substrate, by machining; and then growing a diamond single crystal by vapor phase synthesis.Type: GrantFiled: March 27, 2006Date of Patent: April 28, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
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Patent number: 7524373Abstract: The invention provides a method to enforce face-to-face stacking of organic semiconductors in the solid state that employs semiconductor co-crystal formers (SCCFs), to align semiconductor building blocks (SBBs). Single-crystal X-ray analysis reveals n-orbital overlap optimal for organic semiconductor device applications.Type: GrantFiled: January 30, 2006Date of Patent: April 28, 2009Assignee: University of Iowa Research FoundationInventors: Leonard R. MacGillivray, Anatoliy N. Sokolov
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Patent number: 7507293Abstract: Fabrication of a photonic crystal is described. A patterned array of nanowires is formed, the nanowires extending outward from a surface, the nanowires comprising a catalytically grown nanowire material. Spaces between the nanowires are filled with a slab material, the patterned array of nanowires defining a patterned array of channels in the slab material. The nanowire material is then removed from the channels.Type: GrantFiled: March 31, 2005Date of Patent: March 24, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Zhiyong Li, R. Stanley Williams, M. Saif Islam, Philip J. Kuekes
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Patent number: 7494546Abstract: The present invention describes use of electron beam evaporation method for fabrication of group III-nitride thin films. The fabricated thin films found to have desirable crystalline and optical properties. These films and their properties could be used for protecting electronic devices under space radiation applications such as solar cell operating in space.Type: GrantFiled: July 16, 2007Date of Patent: February 24, 2009Assignee: Blue Wave Semicodnuctors, Inc.Inventors: Ratnakar D. Vispute, Evan Bertrue Jones
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Patent number: 7491269Abstract: The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.Type: GrantFiled: December 3, 2002Date of Patent: February 17, 2009Assignee: ThalesInventors: Pierre Legagneux, Didier Pribat, Yannig Nedellec
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Patent number: 7488385Abstract: The invention concerns the preparation of gallium nitride films by epitaxy with reduced defect density levels. It concerns a method for producing a gallium nitride (GaN) film by epitaxial deposition of GaN. The invention is characterized in that it comprises at least a step of epitaxial lateral overgrowth and in that it comprises a step which consists in separating part of the GaN layer from its substrate by embrittlement through direct ion implantation in the GaN substrate. The invention also concerns the films obtainable by said method as well as the optoelectronic and electronic components provided with said gallium nitride films.Type: GrantFiled: May 28, 2003Date of Patent: February 10, 2009Assignee: LumilogInventors: Hacène Lahreche, Gilles Nataf, Bernard Beaumont
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Patent number: 7481880Abstract: A method of crystallizing amorphous silicon includes forming an amorphous silicon layer on a substrate, placing a mask over the substrate including the amorphous silicon layer, and applying a laser beam onto the amorphous silicon layer through the mask to form a first crystallized region, the laser beam having an energy intensity high enough to completely melt the amorphous silicon layer, wherein the mask comprises a base substrate, a phase shift layer on the base substrate, having a plurality of first stripes having a first width separated by slits, and a blocking layer overlapping the phase shift layer, having a plurality of second stripes having a second width narrower than the first width, the second stripes being parallel to the first stripes.Type: GrantFiled: January 25, 2006Date of Patent: January 27, 2009Assignee: LG Display Co., Ltd.Inventor: Kwang-Jo Hwang
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Patent number: 7479188Abstract: A process for producing an inexpensive large high-quality GaN substrate which comprises forming a MgO buffer layer on a high-quality substrate, generating a ZnO layer on the MgO buffer layer while performing polarity control, growing a GaN layer on the ZnO layer while performing polarity control, and melting the ZnO layer, thereby producing a GaN substrate.Type: GrantFiled: March 19, 2004Date of Patent: January 20, 2009Assignee: Tohoku Techno Arch Co., Ltd.Inventors: Takafumi Yao, Takuma Suzuki, Hang-ju Ko, Agus Setiawan
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Patent number: 7465354Abstract: A process, for patterning a thin film that is highly resistant to conventional etching processes and that is to be deposited at a high substrate temperature, is disclosed. The process uses a liftoff method wherein a refractory material has been substituted for the conventional organic resin. The method is particularly useful for the fabrication of tunable microwave devices and ferroelectric memory elements.Type: GrantFiled: March 8, 2005Date of Patent: December 16, 2008Assignee: National University of SingaporeInventors: Chong Kim Ong, Chin Yaw Tan
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Patent number: 7462239Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.Type: GrantFiled: May 12, 2006Date of Patent: December 9, 2008Assignee: ASM America, Inc.Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
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Patent number: 7459025Abstract: Systems and methods for transferring a thin film from a substrate onto another substrate, a layer of the same area as the substrate, of a thickness from sub-micron to tens of micron, and of the thickness and flatness required by VLSI and MEMS applications, and with sufficiently low defect density in the transferred layer are disclosed. The method enables separating a solid layer from a supply substrate and optionally transferring the solid layer onto a target substrate. The method generally includes providing the solid layer on a hydrogen recombination region containing hydrogen-recombination-dopant at a concentration higher than that of the solid layer. The supply substrate includes the solid layer, a mother substrate, and the hydrogen recombination region. The hydrogen recombination region may form a part of the mother substrate or may be separate therefrom.Type: GrantFiled: June 3, 2003Date of Patent: December 2, 2008Inventor: Tien-Hsi Lee
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Patent number: 7455729Abstract: The invention concerns a method for preparing gallium nitride films by vapour-phase epitaxy with low defect densities. The invention concerns a method for producing a gallium nitride (GaN) film from a substrate by vapour-phase epitaxy deposition of gallium nitride. The invention is characterized in that the gallium nitride deposition comprises at least one step of vapour-phase epitaxial lateral overgrowth, in that at least one of said epitaxial lateral overgrowth steps is preceded by etching openings either in a dielectric mask previously deposited, or directly into the substrate, and in that it consists in introducing a dissymmetry in the environment of dislocations during one of the epitaxial lateral overgrowth steps so as to produce a maximum number of curves in the dislocations, the curved dislocations not emerging at the surface of the resulting gallium nitride layer. The invention also concerns the optoelectronic and electronic components produced from said gallium nitride films.Type: GrantFiled: July 24, 2003Date of Patent: November 25, 2008Assignee: LumilogInventors: Bernard Beaumont, Pierre Gibart, Jean-Pierre Faurie
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Patent number: 7445673Abstract: Gallium nitride substrates are grown by epitaxial lateral overgrowth using multiple steps. On a masked substrate having openings areas, selective growth produces first triangular stripes in which most of the threading dislocations are bent at 90°. In a second step, growth conditions are changed to increase the lateral growth rate and produce a flat (0001) surface. At this stage the density of dislocations on the surface is <5×107 cm 2. Dislocations are primarily located at the coalescence region between two laterally grown facets pinching off together. To further decrease the dislocation density a second masking step is achieved, with the openings exactly located above the first ones. Threading dislocations (TDs) of the coalescence region do not propagate in the top layer. Therefore the density of dislocations is lowered below <1×107 cm lover the entire surface.Type: GrantFiled: May 18, 2004Date of Patent: November 4, 2008Assignee: LumilogInventors: Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart
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Publication number: 20080265264Abstract: A method for growing a ?-Ga2O3 single includes preparing a ?-Ga2O3 seed crystal and growing the ?-Ga2O3 single crystal from the ?-Ga2O3 seed crystal in a predetermined direction.Type: ApplicationFiled: June 12, 2008Publication date: October 30, 2008Applicant: Waseda UniversityInventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Patent number: 7442254Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.Type: GrantFiled: November 14, 2006Date of Patent: October 28, 2008Assignee: Nichia CorporationInventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho
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Patent number: 7438762Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.Type: GrantFiled: August 24, 2006Date of Patent: October 21, 2008Assignee: Stanley Electric Co., Ltd., Tokyo Denpa Co., Ltd., and Tohoku UniversityInventors: Hiroyuki Kato, Michihiro Sano, Katsumi Maeda, Hiroshi Yoneyama, Takafumi Yao, Meoung Whan Cho
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Patent number: 7438759Abstract: An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.Type: GrantFiled: November 1, 2005Date of Patent: October 21, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Fengyan Zhang, Robert A. Barrowcliff, Jong-Jan Lee, Sheng Teng Hsu
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Patent number: 7431767Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.Type: GrantFiled: November 27, 2006Date of Patent: October 7, 2008Assignee: ASM America, Inc.Inventor: Ivo Raaijmakers
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Patent number: 7427326Abstract: A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.Type: GrantFiled: November 16, 2006Date of Patent: September 23, 2008Assignee: Cree, Inc.Inventors: Joseph J. Sumakeris, Ranbir Singh, Michael James Paisley, Stephan Georg Mueller, Hudson M. Hobgood, Calvin H. Carter, Jr., Albert Augustus Burk, Jr.
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Patent number: 7416606Abstract: The invention relates to a method of forming a layer of silicon carbide on a silicone wafer. The method includes the following steps: depositing an anti-carburation mask on the wafer using an essentially-check pattern; performing a carburation step under conditions such that the residual stress takes the form of extension and compression respectively; removing the mask; and form of extension and compression respectively; removing the mask; and performing a carburation step under conditions such that the residual stress takes form of compression and extension respectively.Type: GrantFiled: May 5, 2004Date of Patent: August 26, 2008Assignee: Centre National de la Recherche ScientifiqueInventor: André Leycuras
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Publication number: 20080197339Abstract: A nanoscale nanocrystal which may be used as a reciprocating motor is provided, comprising a substrate having an energy differential across it, e.g. an electrical connection to a voltage source at a proximal end; an atom reservoir on the substrate distal to the electrical connection; a nanoparticle ram on the substrate distal to the atom reservoir; a nanolever contacting the nanoparticle ram and having an electrical connection to a voltage source, whereby a voltage applied between the electrical connections on the substrate and the nanolever causes movement of atoms between the reservoir and the ram. Movement of the ram causes movement of the nanolever relative to the substrate. The substrate and nanolever preferably comprise multiwalled carbon nanotubes (MWNTs) and the atom reservoir and nanoparticle ram are preferably metal (e.g. indium) deposited as small particles on the MWNTs.Type: ApplicationFiled: September 19, 2005Publication date: August 21, 2008Inventors: Brian Christopher Regan, Alexander K. Zettl, Shaul Aloni
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Publication number: 20080188064Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.Type: ApplicationFiled: October 5, 2007Publication date: August 7, 2008Inventors: Lars Ivar SAMUELSON, Bjorn Jonas Ohlsson
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Patent number: 7407549Abstract: A diamond single crystal composite substrate which are constructed from a plurality of diamond single crystal substrates with uniform plane orientations disposed side by side and integrated overall by growing diamond single crystals thereon by vapor phase synthesis, in which the deviation of the plane orientation of the main plane of each of said plurality of diamond single crystal substrates, excluding one diamond single crystal substrate, from the {100} plane is less than 1 degree, the deviation of the plane orientation of the main plane of the excluded one substrate from the {100} plane is 1 to 8 degrees, said one diamond single crystal substrate is disposed in the outermost circumferential part when the diamond single crystal substrates are disposed side by side, and is disposed so that the <100> direction in the main plane of said one substrate faces in the outer circumferential direction of the disposed substrates, and diamond single crystals are then grown by vapor phase synthesis so that the diaType: GrantFiled: November 4, 2004Date of Patent: August 5, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
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Patent number: 7407548Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.Type: GrantFiled: August 11, 2004Date of Patent: August 5, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Ian Cayrefourcq, Mark Kennard
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Patent number: 7404858Abstract: A method for epitaxial growth of silicon carbide using chemical vapor deposition (CVD) is provided. This method utilizes halogenated carbon precursors and control of the gas-phase interaction of halogen-containing intermediate chemical products involving silicon and carbon, which ensures quality and homogeneity across the silicon carbide crystals. It also ensures a possibility to achieve device-quality epitaxial layers at lower growth temperatures as well as on on-axis or low off-angle substrate surfaces. The growth method can be applied to forming SiC device regions of desirable shape and dimensions by restricting the growth into windows formed in non-silicon carbide region on the top of SiC substrate. Application of the methods described herein will greatly benefit the production of high quality silicon carbide materials and devices.Type: GrantFiled: September 15, 2006Date of Patent: July 29, 2008Assignee: Mississippi State UniversityInventor: Yaroslav Koshka
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Patent number: 7399356Abstract: A film structure of a ferroelectric single crystal which can be beneficially used in the fabrication of high-performance electric and electronic parts and devices is prepared by forming an electrode layer having a perovskite crystal structure on a substrate made of a silicon or ferroelectric single crystal optionally polished to have a off-axis crystal structure, and epitaxially growing a layer of a ferroelectric single crystal thereon by pulsed laser deposition (PLD) or metallorganic chemical vapor deposition (MOCVD).Type: GrantFiled: July 14, 2003Date of Patent: July 15, 2008Assignee: Ibule Photonics, Inc.Inventors: Jaehwan Eun, Sang-Goo Lee, Hyeongjoon Kim, Minchan Kim
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Publication number: 20080163814Abstract: A method of reducing threading dislocation densities in non-polar such as a- {11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.Type: ApplicationFiled: December 11, 2007Publication date: July 10, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Kwang Choong Kim, Mathew C. Schmidt, Feng Wu, Asako Hirai, Melvin B. McLaurin, Steven P. DenBaars, Shuji Nakamura, James S. Speck
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Patent number: 7396409Abstract: By uniformly forming an indefinite number of microscopic acicular crystals on a surface of a silicon substrate so as to be perpendicular to the surface of the substrate by plasma CVD method using a catalyst, it is possible to reliably, homogeneously and massively form an ultramicroscopic acicular silicon crystal having a substantial cone shape tapered so as to have a radius of curvature of not less than 1 nm to no more than 20 nm at its tip end and having a diameter of bottom surface of not less than 10 nm, and a height equivalent to or more than the diameter of bottom surface, at a desired location.Type: GrantFiled: September 4, 2003Date of Patent: July 8, 2008Assignees: Covalent Materials Corporation, Techno Network Shikoku Co., Ltd.Inventors: Akitmitsu Hatta, Hiroaki Yoshimura, Keiichi Ishimoto, Hiroaki Kanakusa, Shinichi Kawagoe
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Patent number: 7396410Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.Type: GrantFiled: December 22, 2006Date of Patent: July 8, 2008Assignee: Cree, Inc.Inventors: Christer Hallin, Heinz Lendenmann
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Patent number: 7393411Abstract: A method for growing a ?-Ga2O3 single crystal hardly cracking and having a weakened twinning tendency and an improved crystallinity, a method for growing a thin-film single crystal with high quality, a GazO3 light-emitting device capable of emitting a light in the ultraviolet region, and its manufacturing method are disclosed. In an infrared-heating single crystal manufacturing system, a seed crystal and polycrystalline material are rotated in mutually opposite directions and heated, and a ?-Ga2O3 single crystal is grown in one direction selected from among the a-axis <100> direction, the b-axis <010> direction, and the c-axis <001> direction. A thin film of a ?-Ga2O3 single crystal is formed by PLD. A laser beam is applied to a target to excite atoms constituting the target Ga atoms are released from the target by thermal and photochemical actions. The free Ga atoms are bonded to radicals in the atmosphere in the chamber.Type: GrantFiled: February 16, 2004Date of Patent: July 1, 2008Assignee: Waseda UniversityInventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Publication number: 20080149021Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Patent number: 7387678Abstract: A GaN substrate comprises a GaN single crystal substrate, an AlxGa1-xN intermediate layer (0<x?1) epitaxially grown on the substrate, and an GaN epitaxial layer grown on the intermediate layer. The intermediate layer is made of AlGaN and this AlGaN grows over the entire surface of the substrate with contaminants thereon and high dislocation regions therein. Thus, the intermediate layer is normally grown on the substrate, and a growth surface of the intermediate layer can be made flat. Since the growth surface is flat, a growth surface of the GaN epitaxial layer epitaxially grown on the intermediate layer is also flat.Type: GrantFiled: June 25, 2004Date of Patent: June 17, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Eiryo Takasuka, Masahiro Nakayama, Masaki Ueno, Kouhei Miura, Takashi Kyono
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Patent number: 7384479Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layer with a thickness of about 2 molecular layers or less.Type: GrantFiled: March 16, 2005Date of Patent: June 10, 2008Assignee: Ricoh Company, Ltd.Inventors: Naoto Jikutani, Shunichi Sato, Takashi Takahashi
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Patent number: 7381397Abstract: Methods and apparatus for preconditioning a lithium niobate or lithium tantalate crystal. At least a portion of a surface of the crystal is covered with a condensed material including one or more active chemicals. The crystal is heated in a non-oxidizing environment above an activating temperature at which the active chemicals contribute to reducing the crystal beneath the covered surface portion. The crystal is cooled from above the activating temperature to below a quenching temperature at which the active chemicals become essentially inactive for reducing the crystal.Type: GrantFiled: December 2, 2005Date of Patent: June 3, 2008Assignee: Crystal Technology, Inc.Inventors: Dieter Hans Jundt, Maria Claudia Custodio Kajiyama
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Publication number: 20080107876Abstract: Disclosed herein is a method of selectively growing zinc oxide microstructures and the zinc oxide microstructures prepared using the method. The method includes the steps of applying an organic material or an inorganic material on a substrate, forming a pattern having a predetermined specific location and a predetermined interval on the substrate using a physical or chemical etching method, and selectively growing zinc oxide microstructures at the location where the pattern is formed using various growth methods such as hydro-thermal synthesis, physical vapor deposition, chemical vapor deposition method or the like.Type: ApplicationFiled: March 27, 2007Publication date: May 8, 2008Applicants: POSTECH FOUNDATION, POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: Gyu-chul Yi, Yong-jin Kim, Chul-ho Lee
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Patent number: 7368014Abstract: A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer thick over the substrate. At a second temperature different from the first temperature, the first layer may be contacted with a second precursor, chemisorbing a second layer at least one monolayer thick on the first layer. Temperature may be altered by adding or removing heat with a thermoelectric heat pump. The altering the substrate temperature may occur from the first to the second temperature. The second layer may be reacted with the first layer by heating to a third temperature higher than the second temperature. A deposition method may also include atomic layer depositing a first specie of a substrate approximately at an optimum temperature for the first specie deposition.Type: GrantFiled: August 9, 2001Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventor: Trung Tri Doan
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Patent number: 7361222Abstract: A method and a device to grow from the vapor phase, a single crystal of either SiC, a group III-nitride, or alloys thereof, at a growth rate and for a period of time sufficient to produce a crystal of preferably several centimeters length. The diameter of the growing crystal may be controlled. To prevent the formation of undesirable polycrystalline deposits on surfaces in the downstream vicinity of the single crystal growth area, the local supersaturation of at least one component of the material grown is lowered by introducing a separate gas flow comprising at least one halogen element or a combination of said halogen and hydrogen species.Type: GrantFiled: April 23, 2004Date of Patent: April 22, 2008Assignee: Norstel ABInventors: Erik Janzén, Peter Råback, Alexandre Ellison
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Patent number: 7357837Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.Type: GrantFiled: October 24, 2003Date of Patent: April 15, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto
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Patent number: 7354477Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: September 9, 2004Date of Patent: April 8, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7338554Abstract: The invention relates to a process for synthesizing nanorods of a carbide of one metal M1 on a substrate, which comprises: a) the deposition, on the substrate, of a layer of nanocrystals of oxide of the metal M1 and nanocrystals of oxide of at least one metal M2 different from metal M1, the M1 metal oxide nanocrystals being dispersed within this layer; b) the reduction of the M1 and M2 metal oxide nanocrystals into corresponding metal nanocrystals; and c) the selective growth of the M1 metal nanocrystals. The invention also relates to a process for growing nanorods of a carbide of one metal M1 on a substrate from nanocrystals of this metal, to the substrates thus obtained and to their applications: fabrication of Microsystems provided with chemical or biological functionalities, in particular the fabrication of biosensors; electron emission sources, for example for flat television or computer screens; etc.Type: GrantFiled: December 4, 2003Date of Patent: March 4, 2008Assignee: Commissariat a L'Energie AtomiqueInventors: Marc Delaunay, Francoise Vinet
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Patent number: 7335255Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.Type: GrantFiled: November 26, 2003Date of Patent: February 26, 2008Assignee: Semiconductor Energy Laboratory, Co., Ltd.Inventors: Shinji Maekawa, Hidekazu Miyairi
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Patent number: 7332030Abstract: Process for the treatment of a component, at least one zone to be treated of which located in the depth of this component at a certain distance from the surface thereof, has at least one property that can be modified when this zone is subjected to a thermal energy density above a specified treatment level, comprises: placing the component to be treated at a thermal energy level below the specified level; and subjecting, through its aforementioned surface, for a specified time and in the form of at least one pulse, the component to a power flux generated by a particle emission unit, this emission unit being regulated so as to produce a thermal energy density that is concentrated on or has a localized maximum in the zone to be treated and reaching, in at least part of this zone, a level above the specified treatment level.Type: GrantFiled: January 15, 2003Date of Patent: February 19, 2008Inventor: Michel Bruel