Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.

Abstract: A socket comprises a housing made of an insulating board and a plurality of contacts arranged on a first surface of the housing. The housing has a plurality of passageways each extending through the housing and having an inner wall surface plated with a conductive material. The housing also has a conductive pad formed on the first surface of the housing that is electrically continuous with the conductive material of the inner wall surface. Each of the contacts includes a contact portion positioned above the first surface of the housing and configured to be elastically deformed by a contact pad electrically connected with the contact, an insertion portion inserted into one of the passageways and configured to be elastically deformed and pressed by the inner wall surface of the passageway, and a joint portion joined to the conductive pad.

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

Abstract: An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.

Abstract: A semiconductor wiring substrate includes a first wiring layer, a second wiring layer stacked on the first wiring layer, and a dielectric layer sandwiched between the first wiring layer and the second wiring layer. The first wiring layer includes first signal lines and first grounding lines which are interleaved and spaced apart in the first wiring layer. The second wiring layer includes second signal lines and second grounding lines which are interleaved and spaced apart in the second wiring layer. An orthographic projection of one of the second signal lines to the first wiring layer is located between each two adjacent ones of the first signal lines.

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Abstract: A transmission line of the disclosure includes: a first line; a second line having characteristic impedance higher than characteristic impedance of the first line; and a third line. The transmission line transmits a symbol that corresponds to a combination of signals in the first line, the second line, and the third line.

Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.

Abstract: Systems and methods for tightly coupled differential vias are described. the storage system device includes a storage drive and a printed circuit board (PCB) of the storage drive. In some embodiments a first via is connected to a first trace routed on a first layer of the PCB, and a second via is connected to a second trace routed on the first layer of the PCB. In some cases, a distance between the first via and the second via is about 1.5 times or less a spacing between the first trace and the second trace.

Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.

Abstract: According to one embodiment, an electronic device includes a first substrate including a first basement and a first conductive layer, a second substrate including a second basement which is disposed to be apart from the first conductive layer and includes a first surface opposed to the first conductive layer and a second surface opposite to the first surface, and a second conductive layer disposed on the second surface, the second substrate including a first hole passing through the second basement, and a connecting material passing through the first hole to electrically connect the first conductive layer and the second conductive layer, wherein the first hole is shaped as a funnel.

Abstract: A differential signal transmitting circuit board includes a substrate, at least two differential conductive elements, and at least one insulating element. The differential conductive elements are disposed in the substrate. The insulating element is disposed in the substrate. The insulating element is close to or contacted to the differential conductive elements. A material of the substrate has a first equivalent dielectric constant. A material of the insulating element has a second equivalent dielectric constant. The first equivalent dielectric constant is different from the second equivalent dielectric constant.

Abstract: A circuit board includes a board defining a holding slot and a connector. The connector includes a conductive column and a pad fixed to one end of the conductive column. The pad is received within the holding slot. The conductive column is fixed within the board. The pad is soldered to a connecting portion of an electrical component. The pad defines a first through hole receiving solder when the connecting portion of the electrical component is soldered to the pad.

Abstract: A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.

Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.

Abstract: Various circuit boards and systems are disclosed. In one aspect a system includes a circuit board and n differential signal via pairs. Each of the n differential signal via pairs has a first signal via and a second signal via and an electrical wall between the first signal via and the second signal via. There is a midline between every two adjacent differential via pairs. There are n ground return path vias. Each of the n ground return path vias is positioned substantially along one of the midlines and not on one of the electrical walls.

Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1, U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.

Abstract: A resin multilayer substrate includes a laminate including a plurality of resin layers and an interlayer connecting conductor which extends through at least one of the plurality of resin layers and is directly exposed to an outside of the laminate.

Abstract: A first land and a first ground pattern generate a first parasitic capacitance CLAND by capacitive coupling with a first insulating layer interposed therebetween. Then, the first parasitic capacitance CLAND is defined as a predetermined capacitance that suppresses an impedance of a via part from changing due to a change in an inductance component of the via part with respect to a first transmission line. As a result, it is possible to match the impedance of the via part with a impedance of the first transmission line by adjusting the first parasitic capacitance CLAND caused by the first land and the first ground pattern. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate from deteriorating without requiring the disposition of cavities such as through holes in the multilayer substrate.

Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.

Abstract: A carrier base material-added wiring substrate includes a wiring substrate and a carrier base material. The wiring substrate includes an insulation layer, a wiring layer arranged on a lower surface of the insulation layer, and a solder resist layer that covers the lower surface of the insulation layer and includes an opening that exposes a portion of the wiring layer as an external connection terminal. The carrier base material is adhered by an adhesive layer to the solder resist layer. The carrier base material includes an opening that is in communication with the opening of the solder resist layer and exposes the external connection terminal. The opening of the carrier base material has a diameter that is smaller than that of the opening of the solder resist layer.

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.

Abstract: A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.

Abstract: An electronic-component mount substrate includes a substrate having a first principal surface and a second principal surface opposite to the first principal surface; a mount electrode for mounting an electronic component on the first principal surface, the mount electrode having a first slit and sandwiching the first slit; a plane electrode surrounding the mount electrode in a plan view and having a second slit; a connection electrode connecting the mount electrode with the plane electrode; and an outer electrode on the second principal surface. The connection electrode overlaps the outer electrode and an outer edge of the outer electrode surrounds the connection electrode in a perspective plan view.

Abstract: A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-m

Abstract: Dynamic electronic printed circuit board (PCB) design is provided. A test net on a PCB is dynamically created utilizing a first rule defining a net parameter and a second rule defining a padstack geometric parameter. A first evaluation of one or more nets having a first padstack is performed against the first rule. A second evaluation of both the first padstack and a reference padstack determined to be adjacently positioned to the first padstack is performed against the second rule. Based on the evaluations, a potential test net having a potential test padstack is dynamically selected from the evaluated nets. The selected potential test net is dynamically transformed into the test net. The dynamic transformation includes modifying the potential test padstack and/or the reference padstack utilizing the second rule. The dynamic creation of the test net improves the efficiency of electronic PCB design by mitigating time and footprint consumption.

Abstract: A multilayer substrate is manufactured by first manufacturing a first substrate by stacking and hot-pressing resin base materials of the first substrate and then adjacently stacking and hot-pressing the first substrate and resin base materials that constitute a second substrate at a position overlapping with each other in a stacking direction. The position in the stacking direction between the resin base materials in the first substrate is located at almost a middle position in the stacking direction of a resin base material of the second substrate, and is different from the position between the layers of the resin base materials of the second substrate.

Abstract: The flexible printed circuit board includes a base layer, a first circuit layer and a second circuit layer, the first circuit and the second circuit layer formed on both sides of the base layer; conducting holes extending through the base layer and the first copper layer, the conducting holes include annular copper ring embedded in the first circuit layer. A height difference between a surface of the annular copper ring and a surface of the first circuit layer is in a range from 0 to 3 micrometers. A method for manufacturing the flexible printed circuit board is also provided.

Abstract: A structure can include a first element and a carrier bonded to the first element along an interface. A waveguide can be defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel, as viewed from a side cross-section of the structure. Various millimeter-wave or sub-terahertz components or circuit structures can also be created based on the waveguide structures disclosed herein.

Abstract: An electrical contact pad for electrically contacting a connector includes a first region having a first length in a longitudinal direction, and a second region having a second length in the longitudinal direction that is greater than the first length. The first region is arranged to contact a first arm of the connector and the second region is arranged to contact a second arm of the connector. The first length being smaller than the second length results in a beneficial increases the impedance of the electrical contact pad. A chamfered edge of the contact pad results in an additional beneficial increase in the impedance of the electrical contact pad.

Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.

Abstract: A flexible display device, a flexible display device fabrication method and an electronic device are provided. The flexible display device comprises a flexible display panel having a first surface for displaying images; a flexible insulating layer disposed on the first surface of the flexible display panel and divided into a plurality of flexible insulating blocks; and a touch control unit disposed on the flexible insulating layer and comprising a first touch control electrode layer in direct contact with the flexible insulating layer. The first touch control electrode layer includes a plurality of first touch control electrodes. Any one of the plurality of flexible insulating blocks corresponds to at least one of the plurality of first touch control electrodes. In a direction perpendicular to the flexible display panel, a gap between any two adjacent flexible insulating blocks overlaps with a gap between two adjacent first touch control electrodes.

Abstract: In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.

Abstract: There is provided an optical module including an optical subassembly including an optical element, a printed circuit board, and a connection substrate. The connection substrate includes a first connection portion connected to a first signal line conductor strip disposed on a first surface and a first ground conductor layer disposed on a second surface. The first connection portion includes a first signal line pad portion, a first ground pad portion, both disposed on the first surface, a second signal line pad portion disposed, and a second ground pad portion, both disposed on the second surface. In the connection substrate, a distance between the first signal line pad portion and the first ground pad portion in a first region is narrower than that in a second region farther from an inner end portion on the gap portion side than the first region in plan view.

Abstract: A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

Abstract: One object is to provide a laminated inductor having a reduced thickness without reduction in the magnetic characteristic and the insulation quality. The laminated inductor includes a first magnetic layer, an internal conductor, second magnetic layers, third magnetic layers, and a pair of external electrodes. The first magnetic layer includes three or more magnetic alloy particles arranged in the thickness direction and an oxide film binding the magnetic alloy particles together and containing Cr. The three or more magnetic alloy particles have an average particle diameter of 4 ?m or smaller. The internal conductor includes a plurality of conductive patterned portions electrically connected to each other via the first magnetic layer. The second magnetic layers are composed of magnetic alloy particles and disposed around the conductive patterned portions. The third magnetic layers are composed of magnetic alloy particles and disposed so as to be opposed to each other in thickness direction.

Abstract: A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.

Abstract: An electronic component built-in substrate includes an insulating base material having a first surface and a second surface opposite to the first surface, an electronic component embedded in the insulating base material and having an electrode on a side surface thereof, a first wiring layer embedded in an area outside the electrode of the electronic component in the insulating base material with a surface of the first wiring layer being exposed from the first surface of the insulating base material, a via conductor reaching from the second surface of the insulating base material to a side surface of the electrode of the electronic component and the first wiring layer, and a second wiring layer formed on the second surface of the insulating base material and connected to the via conductor.

Abstract: A multilayer substrate includes plural layers of circuit patterns. Each circuit pattern includes a ground conductor surrounding a wiring region provided with a conductive wiring pattern. Each ground conductor includes a slit connecting between the outside of the multilayer substrate and the wiring region. In the multilayer substrate, the slit of the ground conductor provided at one of adjacent two layers of the circuit patterns and the slit of the ground conductor provided at the other circuit pattern are formed at positions not overlapping with each other. That is, these slits are formed at such positions that a view in an upper-to-lower direction is blocked. The shape of the slit of each ground conductor is in such a shape that a view from an end side of the multilayer substrate to a wiring region side is blocked.

Abstract: The embodiments herein relate to an apparatus and medium for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The apparatus and medium implement a step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.

Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

Abstract: The present invention provides an apparatus and/or method for modular, scalable and nestable parallel data processing and process control systems from molecular to module/enclosure level, comprised of calculable inter- and intra-modular processing time standards and shorter look-ahead propagation paths; based on regular and irregular hexagonal and dodecagonal prisms, derivative dumbbells and variants as actual and/or approximated tilings/tessellations which may be arranged in columns, rows, stacks and arrays with or without rounding and/or a sliding fit. Non-sliding fit systems are fundamentally solid. Sliding fit systems modules have a central cavity with systems as follows: cage assembly, optional patch panels, anchoring, thermal management, interconnect enclosures, power, hot swap, fail over, positioning, and interconnects with optional quick disconnects and retractors.

Abstract: An inductor includes a body including a coil part therein. The coil part includes a support member and first and second coil patterns respectively formed on an upper surface and a lower surface of the support member, and 1.15?b/a?1.45, where a is a length from a central plane between the upper surface and the lower surface of the support member to an upper surface of the body, and b is a length from the central plane of the support member to a lower surface of the body.

Abstract: Reliability of a plating process and reliability of a component manufactured through the plating process can be improved by suppressing peeling between plating layers formed by electroless plating. In a plating method, a plated component manufactured by the plating method, and a plating system 1 configured to manufacture the plated component by the plating method, a second electroless plating layer 39, which is made of a copper alloy and formed by the electroless plating, is formed on a surface of a first electroless plating layer 38 formed by the electroless plating. The first electroless plating layer 38 is a barrier layer configured to suppress diffusion of copper and is made of cobalt or a cobalt alloy. The second electroless plating layer 39 is a seed layer for forming an electrolytic plating layer of copper on a surface thereof and is made of an alloy of copper and nickel.

Abstract: Package substrate and a method of manufacturing the same is disclosed. The package substrate includes an insulating layer having first circuit patterns embedded in a first surface of the insulating layer, and a protruded circuit pattern formed above at least one of the embedded first circuit patterns, wherein a width of the protruded circuit pattern is greater than a width of each of the embedded first circuit patterns. Accordingly, a flip chip and a wire bonding chip may be installed at the same time owing to an embedded structure of circuit pattern and a protruded structure of circuit pattern realized together on a surface where an electronic component is to be installed. Moreover, a fine circuit pattern may be formed, and a surface treatment layer may be selectively formed at desired portions without forming an additional seed layer for electroplating, thereby possibly simplifying manufacturing processes and saving manufacturing costs.

Abstract: An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.

Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include forming a first sub-laminated board comprising a first horseshoe structure that is disposed on a top surface of a first outer ground structure, forming a second sub-laminated board comprising a second horseshoe structure disposed on a second outer ground structure, wherein the second sub-laminated board comprises a stripline trace on a top surface of the second sub-laminated board, and laminating the first sub-laminated board to the second sub-laminated board, wherein the first and second horseshoe structures are in contact with each other during the lamination process.

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A dicing process is performed, such that at least one slit is formed in the glass film. A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on the glass film. A polymer layer is formed on the first circuit layer. The polymer layer covers surfaces of the first circuit layer and the glass film. A plurality of second conductive vias are formed in the polymer layer. A second circuit layer is formed on the polymer layer, such that a first circuit board structure is formed. A singulation process is performed, such that the first circuit board structure is divided into a plurality of second circuit board structures.

Abstract: A semiconductor package structure includes a first dielectric layer, a conductive element, a first circuit structure, a semiconductor die and an encapsulant. The first dielectric layer defines at least one through hole. The conductive element is disposed in the through hole and including a first portion and a second portion. A first surface of the first portion is substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer. The first circuit structure is disposed on the first dielectric layer. The semiconductor die is electrically connected to the first circuit structure. The encapsulant covers the semiconductor die.