Abstract: In a manufacturing method for a member for a semiconductor manufacturing device, a metal terminal and a ceramic member are joined by using a paste that contains a resin and a metal particle(s), and a metal fine particle(s) that has/have a particle size(s) of 100 nm or less in the metal particle(s) account(s) for 1% by mass or more of 100% by mass of the metal particle(s). A member for a semiconductor manufacturing device includes a metal terminal, a ceramic member, and a joining part that connects the metal terminal and the ceramic member. The joining part contains a metal particle(s).

Abstract: A circuit structure includes a substrate integrated waveguide, a substrate disposed on the substrate integrated waveguide, a waveguide signal feeding element and a ring-shaped conductive element. The substrate integrated waveguide includes another substrate having a waveguide transmitting region, two conductive layers disposed on this substrate and covering the waveguide transmitting region, and at least one waveguide conductive element passing through this substrate and electrically connected to the two conductive layers. The at least one waveguide conductive element surrounds the waveguide transmitting region. One of the conductive layers is located between the two substrates. The waveguide signal feeding element passes through one substrate and one conductive layer between the substrates, and the waveguide signal feeding element extends to the waveguide transmitting region. The waveguide signal feeding element is electrically insulated from one conductive layer.

Abstract: A method of the present disclosure includes: plating a plurality of substrates using a substrate holder; determining a total number of substrates that have been plated using the substrate holder until a failure occurs in the substrate holder; determining a first processable number and a second processable number; generating a first data set constituted by a combination of first condition data and the first processable number, the first condition data representing a state of a component of the substrate holder; generating a second data set constituted by a combination of second condition data and the second processable number, the second condition data representing a state of a component of the substrate holder; and optimizing a parameter of a prediction model constituted by a neural network using training data including the first data set and the second data set.

Abstract: A method of making a printed circuit board structure including a closed cavity is provided. The method can include the steps of forming a cavity in a core structure of a core layer, laminating each of a top surface and a bottom surface of the core structure with an adhesive layer and a metal layer to prepare a laminate structure and cover the cavity to define a closed cavity. The method also includes forming vias through the laminate structure, and patterning the metal layers in the laminate structure.

Abstract: A ceramic feedthrough assembly has a feedthrough interface sleeve brazed to a ceramic feedthrough body and a housing interface sleeve brazed to the feedthrough interface sleeve. The housing interface sleeve is configured to be integrated within an electronic device and welded to a metal housing to form a hermetically sealed electronic device. The ceramic feedthrough has at least one embedded electrical conductor extending from a first location on the ceramic feedthrough body to a second location on the ceramic feedthrough body. The feedthrough interface sleeve is positioned around the ceramic feedthrough body between the first location and the second location and brazed to the wrap-around metallization. When the metal housing is welded to the housing interface sleeve, the ceramic feedthrough assembly facilitates connection to an electronic circuit hermetically sealed in the electronic device with the metal housing.

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

Abstract: An electronic component comprising a main body part including an insulating layer and a conductor layer laminated alternately. The insulating layer and the conductor layer are partially exposed on a side surface of the main body part in a direction orthogonal to a lamination direction. Also, the side surface of the main body part is provided with a metal film extending in the lamination direction to cover the insulating layer and the conductor layer exposed on the side surface.

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Abstract: A wiring board includes an insulating substrate, at least one external electrode disposed on a first surface of the insulating substrate, and wiring that is disposed in the insulating substrate and that is electrically connected to the at least one external electrode. The wiring includes a portion where an extension direction of the wiring is inclined relative to the first surface of the insulating substrate.

Abstract: A transmission line substrate includes a stacked body that includes insulating base materials, first and second signal lines, and first and second ground conductors. The second signal line is provided on a layer different from the layer of the first signal line and extends in parallel with the first signal line. The first ground conductor is provided on the same layer as the layer of the second signal line and overlapped with the first signal line when viewed in the Z-axis direction. The second ground conductor is provided on the same layer as the layer of the first signal line and overlapped with the second signal line when viewed in the Z-axis direction. A first transmission line includes the first signal line, the first ground conductor, and an insulating base material, and a second transmission line includes the second signal line, the second ground conductor, and the insulating base material.

Abstract: Disclosed herein is an antenna device that includes: a substrate having a plurality of insulating layers laminated in a z-direction; a first ground pattern formed on a first insulating layer; a first radiating conductor pattern formed on a second insulating layer; a second ground pattern constituted by a first via conductor provided so as to penetrate at least two insulating layers; and a second radiating conductor pattern constituted by a second via conductor provided so as to penetrate at least one insulating layer. The first radiating conductor pattern overlaps the first ground pattern in the z-direction. The second radiating conductor pattern overlaps the second ground pattern in a y-direction.

Abstract: A wiring substrate includes a core substrate, and a build-up part laminated on the substrate and including resin insulating layers. The insulating layers include a first insulating layer, the build-up part includes a conductor layer on the first insulating layer, a second insulating layer on the first insulating layer and covering the conductor layer, and a recess penetrating through the second insulating layer and exposing portion of the conductor layer such that the conductor layer includes component mounting region that places an electronic component in the recess and a conductor pad forming bottom surface of the recess, the insulating layers include inorganic filler such that all insulating layers or all insulating layers other than the first insulating layer include the inorganic filler and that inorganic filler content rate of the first insulating layer is lower than inorganic filler content rate of the insulating layers other than the first insulating layer.

Abstract: A method for manufacturing an inductor built-in substrate includes forming openings in a core substrate including a resin substrate and a metal foil laminated on the resin substrate, filling a magnetic resin in the openings formed in the substrate, forming a shield layer including a first plating film on the substrate and on a surface of the magnetic resin such that the shielding layer is formed on the metal foil and on the surface of the magnetic resin, forming first through holes in the substrate, applying a desmear treatment in the first through holes, forming second through holes in the magnetic resin after the desmear treatment, and forming a second plating film on the substrate, on the magnetic resin, and in the first and second through holes such that the second plating film is formed on the shield layer, in the first through holes, and in the second through holes.

Abstract: Systems and methods are provided to produce electromechanical interconnections within integrated circuits (ICs), printed circuit boards (PCBs) and between PCBs and other electronic components such as resistors, capacitors and integrated circuits. Elements include so-called “smart pins” or “neuro-pins” that facilitate electrical pathways in the dimension normal to the plane of a PCB. Smart pins or neuro-pins may be inserted using automated processes that do not require the high temperatures normally associated with soldering. Resultant circuits generally contain a large number of layers that are more compact and more readily constructed compared with conventional PCB-based circuitry.

Abstract: The present invention provides a flexible substrate and a display panel. The flexible substrate comprises a substrate and a plurality of traces. The traces are disposed on the substrate. The substrate is further provided with a plurality of first via holes, and the first via holes are disposed along an extending direction of the traces.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: A coil component includes a body including a plurality of pattern layers and a via electrode layer connecting the respective conductive pattern layers to each other, and external electrodes disposed on an external surface of the body. A cross-sectional shape of the via electrode layer is divided into an upper region and a lower region, a side surface of the upper region has a tapered shape, and a lower surface of the lower region includes a curved portion.

Abstract: A motherboard may utilize a retimer device to condition signals used for high-speed USB data transfers. Motherboard embodiments include a common footprint for USB retiming capabilities. A motherboard that supports high-speed USB transfers, such as transfers of 10 Gbps or greater, utilizes a retimer in the footprint. A motherboard that supports lower-speed USB transfers, such as 5 Gbps, utilizes a passive bridge component in the footprint, where the bridge may be formed from a dielectric substrate. During manufacture of an IHS (Information Handling System) a common motherboard is selected that includes a retimer footprint, where the motherboard includes traces that couple the footprint to a USB connector and traces that couple the footprint to a USB controller. Based on the USB transfer speeds to be supported by the motherboard, a USB retimer or a passive bridge is installed in the retimer footprint.

Abstract: A light emitting device package disclosed to an embodiment of the invention includes a body including an upper surface and a lower surface, the body including a first recess and a second recess concaved from the lower surface toward the upper surface; a light emitting device disposed on the body and including a first bonding portion and a second bonding portion; and first and second conductive portions respectively disposed in the first recess and the second recess, wherein the body includes a first through hole and a second through hole penetrating an upper surface of each of the first recess and the second recess and the upper surface of the body, and wherein each of the first and second conductive portions extends into the first and second through holes and is electrically connected to the first bonding portion and the second bonding portion, respectively.

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A coaxial thru-via conductor and a method of fabricating the coaxial thru-via conductor can provide enhanced operations for semiconductor devices mounted on a substrate.

Abstract: Disclosed is a stretchable substrate including: a via configured to provide an electrical connection between one surface and the other surface of the stretchable substrate; and a buffer shell positioned between the via and the stretchable substrate and having a Young's modulus value that is greater than a Young's modulus value of the stretchable substrate and smaller than a Young's modulus value of the via.

Abstract: A coil electronic component includes a body and external electrodes disposed on an external surface of the body. The body includes a support member including a through-hole, upper and lower coils supported by the support member and including a plurality of coil patterns, a via connecting the upper and lower coils to each other, and an insulating wall supported by the support member and insulating adjacent coil patterns from each other. The via is formed on at least a portion of a interface of the through-hole.

Abstract: A multilayer substrate includes a plurality of insulator layers laminated, a column conductor extending through two or more insulator layers among the plurality of insulator layers. The column conductor includes a first via conductor extending through a first insulator layer and a second via conductor extending through a second insulator layer adjacent to the first insulator layer. Each of the first via conductor and the second via conductor has a tapered shape in which a cross section decreases from one end portion to the other end portion in the lamination direction of the plurality of insulator layers. The first via conductor and the second via conductor are directly bonded to each other at large diameter portions that are end portions with a large cross section or small diameter portions that are end portions with a small cross section.

Abstract: Disclosed are a method for fabricating a printed circuit board wherein through-holes are formed in an organic substrate, followed by forming micro-circuit patterns through sputtering and plating, whereby the printed circuit board has low permittivity properties and enables high-speed processing, and a printed circuit board fabricated thereby. The disclosed method for fabricating a printed circuit board comprises the steps of: preparing a base substrate; forming a through-hole perforating the base substrate; forming a thin seed layer on the base substrate and in the through-hole; forming a thin plate layer on the thin seed layer; and etching the thin seed layer and the thin plate layer to form a micro-circuit pattern, wherein the base substrate is one selected from an organic substrate, FR-4, and Prepreg.

Abstract: A micro LED display panel and a method for fabricating the same are disclosed, and the micro LED display panel includes a TFT back panel, and a micro LED fixed on the TFT back panel, wherein the TFT back panel includes a substrate, and a first insulation layer and a second insulation layer stacked over the substrate in that order, wherein the first insulation layer includes a groove filled with the second insulation layer, and a normal projection of the groove onto the substrate does not overlap with a normal projection of a TFT area in the TFT back panel onto the substrate, wherein the rigidity of the second insulation layer is lower than the rigidity of the first insulation layer.

Abstract: A fabrication method of a panel, a panel and a display device are provided. The fabrication method of the panel includes: forming a first conductive layer on a base substrate by using a patterning process, the first conductive layer including a plurality of first conductive traces provided in a non-working region of the base substrate and a plurality of electrode patterns provided in a working region of the base substrate; forming a plurality of metal traces on the plurality of first conductive traces, wherein, each of the metal traces includes a connection end close to an edge of the working region of the base substrate.

Abstract: Provided is a printed circuit board realizing selective inhibition of electromagnetic noise and enabling high-density arrangement of differential transmission lines without increasing cost. The printed circuit board includes a pair of strip conductors (first layer), a first resonance conductor plate, a ground conductive layer (together with a second layer) including an opening portion, a second resonance conductor plate (third layer), a third resonance conductor plate (fourth layer), first via holes connecting the first and second resonance conductor plates, a second via hole connecting the second and third resonance conductor plates, and third via holes connecting the third resonance conductor plate and the ground conductive layer, wherein a polygon obtained by sequentially connecting centers of the adjacent third via holes overlaps so as to include the first resonance conductor plate, and center-to-center distance between the adjacent third via holes is 0.

Abstract: An insulating circuit substrate includes an insulating layer; and a circuit layer formed on one surface of the insulating layer, in which the insulating layer has a core layer formed of an epoxy resin containing an inorganic filler, and a skin layer formed on the circuit layer side of the core layer and formed of a polyimide resin containing an inorganic filler, an amount of the inorganic filler in the epoxy resin forming the core layer is in a range of 80 vol % or more and 95 vol % or less, and an amount of the inorganic filler in the polyimide resin forming the skin layer is in a range of 10 vol % or more and 30 vol % or less.

Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display apparatus. The array substrate includes a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region. Each data lead corresponds to one pad structure. The pad structure includes at least two pad electrodes insulated from each other. In the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths.

Abstract: A composite electronic component includes a composite body in which a multilayer ceramic capacitor and a ceramic chip are coupled to each other, the multilayer ceramic capacitor including a first ceramic body in which a plurality of dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween are stacked, and first and second external electrodes disposed on both end portions of the first ceramic body, and the ceramic chip being disposed on a lower portion of the multilayer ceramic capacitor and formed of a ceramic material having substantially no piezoelectric property, wherein a ratio (T/L) of thickness (T) of the ceramic chip to length (L) of the multilayer ceramic capacitor is selected to minimize vibration of the ceramic chip.

Abstract: A method of manufacturing a component carrier includes: i) forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, with at least one cavity formed in the stack, ii) forming a cluster by encapsulating a first electronic component and a second electronic component in a common encapsulant, and thereafter iii) placing the cluster in the common encapsulant at least partially into the cavity and v) embedding the cluster in the cavity.

Abstract: A printed circuit board includes a printed circuit board includes a substrate portion having a recess portion and including a first circuit layer, abridge disposed in the recess portion and including an insulating layer and a bridge circuit layer, an insulating material disposed in at least a portion of the recess portion and covering at least a portion of the bridge, a second circuit layer disposed on the insulating material, and a first via penetrating through the insulating material and a portion of the bridge and connecting the second circuit layer and the bridge circuit layer to each other.

Abstract: A semiconductor device includes an insulated circuit board having conductor layers arranged away from each other and bonding materials each provided on the conductor layers; a wiring board having an opposing surface facing the conductor layers and through holes each corresponding to a position of each bonding material; hollow members each having a cylindrical portion and a flanged portion at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, ok cylindrical portions press-fitted into the through holes, and other ends of the cylindrical portions bonded to the conductor layers by the bonding materials; and external connection terminals each inserted into the cavity of each hollow member and bonded to the conductor layers. Each cylindrical portion is inserted into each through hole such that each flanged portion contacts with an upper surface opposed to the opposing surface of the wiring board.

Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.

Abstract: A package substrate includes a wiring substrate comprising an insulating layer, a first wiring layer, and a second wiring layer, wherein the first wiring layer comprises a first pad pattern, and the second wiring layer comprises a second pad pattern; a first passivation layer disposed on the insulating layer, and having a first opening portion passing through a region corresponding to at least a portion of the first pad pattern; a second passivation layer disposed on the insulating layer, and having a second opening portion passing through a region corresponding to at least a portion of the second pad pattern; and a reinforcing layer disposed on the second passivation layer, and having a through portion exposing the second opening portion. An upper surface of the first wiring layer is located in a position higher than a position of the lower surface of the insulating layer.

Abstract: Disclosed are a hole connecting layer manufacturing method, a circuit board manufacturing method and a circuit board. The hole connecting layer manufacturing method comprises: adhering a first insulating dielectric layer, used for laminating and filling, to a daughter board; laminating and solidifying the first insulating dielectric layer on the daughter board; adhering a second insulating dielectric layer, used for laminating and filling, to the first insulating dielectric layer which has been laminated and solidified; manufacturing a first receiving hole on the first insulating dielectric layer and a second receiving hole on the second insulating dielectric layer, wherein the first receiving hole and the second receiving hole are provided vertically opposite to each other; filling both the first receiving hole and the second receiving hole with a conductive medium to complete manufacturing of the hole connecting layer.

Abstract: The present disclosure provides a double-sided two-dimensional coding, includes a transparent medium layer on which a metal layer is plated, and a two-dimensional coding image is fused through the metal layer. The present disclosure also provides a flexible printed circuit and manufacturing method for a double-sided two-dimensional coding. By lasering the metal layer corresponding to the transparent medium layer, the metal layer is fused through to form a two-dimensional coding image, and the transparent medium layer is retained as a carrier of the two-dimensional coding image, and an effect of reading the two-dimensional coding on both sides can be achieved.

Abstract: A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.

Abstract: A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.

Abstract: A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.

Abstract: An array substrate and display apparatus, the array substrate comprising a base substrate (10) and signal lines (VDD, VSS) provided on the base substrate (10), wherein at least one electrically conductive element (12) corresponding to the signal lines (VDD, VSS) is further provided on the base substrate (10), the signal lines (VDD, VSS) are connected in parallel with corresponding electrically conductive elements (12), and the electrically conductive elements (12) corresponding to different signal lines (VDD, VSS) are insulated from one another. Thus, resistance of the signal lines (VDD, VSS) can be reduced and the display effect can be improved.

Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

Abstract: A circuit carrier includes a substrate, a laminar circuit structure, a metal heat slug, a first fixing piece, and a second fixing piece. The laminar circuit structure is disposed over the substrate and includes a plurality of dielectric layers and circuits in the dielectric layers. The metal heat slug is disposed in the laminar circuit structure. The first fixing piece is disposed on the first side of the upper surface of the metal heat slug. The second fixing piece is disposed on the second side of the upper surface of the metal heat slug, wherein the first side is perpendicular to the second side. A method of manufacturing a circuit carrier is also provided herein.

Abstract: A component carrier including a stack with a plurality of electrically insulating layer structures and/or a plurality of electrically conductive layer structures, and a non-uniform magnetic foil integrated in the stack.

Abstract: The heat dissipation of a circuit assembly is improved. A circuit assembly includes: a relay that includes a terminal and generates heat when energized/as a result of energization/due to being energized; a base member to which the relay is attached and in which a through hole is formed; a heat dissipation member that is provided on a side of the base member opposite to a side on which the relay is attached; a first busbar that is connected to the terminal of the relay at a position spaced apart from the base member; and a heat transfer member that is inserted into the through hole so as to be movable in a direction along the axial direction of the through hole, and that comes into contact with the first busbar and the heat dissipation member.

Abstract: A wiring substrate includes a laminate having a through hole and including conductor layers and insulating layers interposed between the conductor layers, solder resist layers formed on the laminate and including a first solder resist layer covering first surface of the laminate and a second solder resist layer covering second surface of the laminate and that the first and second solder resist layers have openings exposing the through hole, and a resin film covering the laminate not covered by the solder resist layers such that the resin film is formed on the first and second surfaces of the laminate inside the openings of the first and second solder resist layers without overlapping with the solder resist layers on the first and second surfaces and that the resin film covers inner wall surface inside the through hole and at least part of the first and second surfaces exposed inside the openings.

Abstract: Provided is a circuit board for reducing a likelihood of so-called through-hole disconnection, and enhancing connection reliability on both sides of a substrate via a through-hole. The circuit board has a substrate with the through-hole, a first conductive part covering an opening of the through-hole on one surface of the substrate in a manner blocking the opening, having a portion inserted into the through-hole from the one surface, and a second conductive part covering a second opening of the through-hole on the other surface of the substrate in a manner blocking the second opening, having a portion inserted into the through-hole from the other surface. The portion of the first conductive part inserted in the through-hole has a columnar shape forming a columnar portion having a diameter smaller than the through-hole.

Abstract: In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment.