Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract: The present invention relates to a device with portions of the device on plural substrate surfaces. The device includes a low resistivity substrate having first and second surfaces with a first electrically-conductive device component disposed over a first surface. An intermediate electrically-insulating layer may be disposed between the electrically-conductive component and the low resistivity substrate. A second electrically-conductive component is disposed over the second surface of the low resistivity substrate. A cavity formed in the low resistivity substrate is at least partially filled with a high resistivity material. One or more electrically-conducting pathways are formed in the high resistivity material electrically connecting the first electrically conductive component and the second electrically-conductive component to form a device. Exemplary devices include inductors, capacitors, antennas and active or passive devices incorporating such devices.

Abstract: A printed wiring board includes an insulative substrate having a penetrating hole, a first conductive layer formed on a first surface of the insulative substrate, a second conductive layer formed on a second surface of the insulative substrate, and a through-hole conductor formed in the penetrating hole through the insulative substrate such that the through-hole conductor is connecting the first conductive layer and second conductive layer. The penetrating hole has a first opening portion formed on a first-surface side of the insulative substrate and a second opening portion formed on a second-surface side of the insulative substrate such that the second opening portion has a depth which is greater than a depth of the first opening portion and the second opening portion has a volume which is greater than a volume of the first opening portion, and the through-hole conductor formed in the second opening portion includes a void portion.

Abstract: A board unit includes a board that has a through hole penetrating the board from a first side of the board to a second side of the board and having a conductive inner wall surface a first electronic component that has a first connection pin to be press-fitted in the through hole from the first side of the board, and a conductive member that is disposed in the through hole to connect the inner wall surface of the through hole to the first connection pin.

Abstract: A bonding pad structure is disclosed, which is composed of two bonding pad units that are symmetrically disposed with respect to an axial line. Each bonding pad units is further composed of at least two bonding pads, i.e. each bonding pad unit is composed of at least one first bonding pad and at least one second bonding pad. In an embodiment, the first bonding pad is arranged next to the axial line and the second bonding pad is arranged at a side of the corresponding first bonding pad away from the axial line while enabling the first bonding pad and the corresponding second bonding pad to be interconnected to each other by a first neck portion. Thereby, a plurality of solder areas of different sizes can be formed by the interconnecting of the at least two bonding pad units that can be used for soldering electronic components of different sizes.

Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the wiring insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked without the adhesive layer interposed between the electrode layer and the wiring layer.

Abstract: A printed wiring board includes a core insulation layer including a resin and having a via conductor through the core insulation layer, a first conductive layer formed on the core layer and including a copper foil and a plated film, an interlayer insulation layer formed on the first layer and including a resin, the interlayer layer having a via conductor through the interlayer layer, and a second conductive layer formed on the interlayer layer and including a copper foil and a plated film. The first layer includes a conductive circuit, the core and interlayer layers have dielectric constants of 4.0 or lower for signal transmission at frequency of 1 GHz and thermal expansion coefficient of 85 ppm/° C. or lower at or below Tg, and the foil of the first layer has thickness greater than thickness of the foil of the second layer.

Abstract: Provided is an optically transparent electrode of which the visibility of the electrode pattern is low. The optically transparent electrode is produced by joining two optically transparent conductive materials each having, on one side of the optically transparent base material, a large lattice 11 formed of a grid-like conductive part and a connector 12 which has at least one connector lattice 16 and which electrically connects adjacent large lattices 11, and is characterized by that the two optically transparent conductive materials are overlapped so that the centers of the connectors 12 thereof approximately coincide, and by that at least one of the two optically transparent conductive materials has a broken lattice 31 where a part of a thin line is broken and electrical conductivity is lost at a position corresponding to the overlapped connectors 12 and/or to a portion surrounded by the large lattice 11 and the connector 12.

Abstract: A method for forming a frame attachment interconnect between a substrate and a frame is disclosed. The method can include applying a composite material (e.g., epoxy-glass prepreg) to a surface of a substrate. The composite material can have one or more holes disposed to substantially align with a corresponding pad on the surface of the substrate. A metal disc is placed in each hole of the composite material on top of the corresponding pad. A frame member can be placed on top of the composite material and the metal discs. The frame member can have one or more pads disposed to substantially align with the metal discs. The substrate, composite material, metal discs and frame combination can be cured in a controlled atmosphere that can include a vacuum and a predetermined temperature to create discrete electrical connections between adjacent pads but with each encapsulated and electrically isolated.

Abstract: A vision regeneration assist apparatus includes: a substrate including electrodes; a control unit; a mount that is formed from a sintered element made of an insulating material, the mount including through holes; an internal conductor that is to be filled into the through holes of the mount to electrically connect the control unit with wires extending from the electrodes. The internal conductor includes: a first conductive material which is to be filled to a predetermined depth from an opening of the through holes at the upper surface of the mount, the first conductive material which takes at least one type of conductive material, which is not fused at a sintering temperature of the mount; and a second conductive material which is formed from a conductive material that is to be filled into a remaining of the through holes, which faces the substrate, the second conductive material exhibiting biocompatibility.

Abstract: A method of manufacturing a wiring substrate, includes forming a laminated body in which a nickel copper alloy layer is formed via an insulating resin layer, on a first wiring layer, forming a via hole reaching the first wiring layer in the nickel copper alloy layer and the insulating resin layer, applying a desmear process to an inside of the via hole, forming a seed layer on the nickel copper alloy layer and an inner surface of the via hole, forming a plating resist in which an opening portion is provided on a part containing the via hole, forming a metal plating layer in the opening portion in the plating resist by an electroplating, removing the plating resist, and forming a second wiring layer by etching the seed layer and the nickel copper alloy layer while using the metal plating layer as a mask.

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 ?m. The platted through hole landing includes an etched pattern and a copper top surface.

Abstract: A circuit including a flexible substrate and at least one electric element attached to the substrate, the substrate including at least one cavity arranged near the electric element and helping to break or distort the electric element in response to a flexion or stretching of the substrate. Application in particular is to the manufacture of tear-proof electronic micromodules.

Abstract: A power distribution network comprises an interposer and a package substrate, each of which has a major upper surface and a major lower surface substantially parallel to the upper surface. A single copper island is formed on the lower surface of the interposer opposite and substantially co-extensive with a single copper island formed on the upper surface of the package substrate. A plurality of leads extend from the copper island on the lower surface of the interposer, each lead coupling to a different silicon through via that extends through the interposer to the upper surface of the interposer. This structure has significant improvements in performance and cost over prior art structures.

Abstract: The printed wiring board 1 includes the metallic substrate 2, the insulating layer 3 provided on the surface of the metallic substrate 2, and the conductive layer 4 formed on the surface of the insulating layer 3. The conductive layer 4 is electrically connected to the metallic substrate 2. A bottomed via hole or a through hole 6 is formed in the insulating layer 3 and the conducive layer 4. The via hole has a bottom in the metallic substrate 2, and has a wall surface in the insulating layer 3 and in the conductive layer 4. The through hole 6 extends through the insulating layer 3, the conductive layer 4, and the metallic substrate 2. Conductive paste 7 fills the bottomed via hole or the through hole 6 to electrically connect the metallic substrate 2 and the conductive layer 4 with each other. The printed wiring board 1 is subjected to a process in which current is applied to the interface between the metallic substrate 2 and the conductive paste 7.

Abstract: A module includes a multilayer body including laminated ceramic green sheets that have been fired, multiple mounting terminals arranged to mount a component thereon, the mounting terminals each including an end surface that is exposed at a main surface of the multilayer body, and multiple via conductors disposed inside the multilayer body so as to correspond to the mounting terminals at positions overlapped by the corresponding mounting terminals when viewed in a plan view. The lengths of the via conductors are adjusted so that predetermined points on the mounting terminals are positioned on the same plane.

Abstract: A flexible printed circuit board, in particular for the spatial connection of electronic components, includes a carrier foil (1), several bonding surfaces (10) arranged on a solder side (4) of the carrier foil (1), and several soldering surfaces (2) arranged on a bonding side (12) of the carrier foil (1) opposite the solder side. The soldering surfaces (2) are connected to the bonding surfaces (10) via electrical strip conductors, and a stiffening plate (3) is inseparably connected to the carrier foil (1) on the solder side thereof.

Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Abstract: The present invention provides a conductive film that includes a substrate, a first matrix layer, a first conductive layer, a second matrix layer, a second conductive layer, a light-shielding layer, a first lead electrode and a second lead electrode. A first grid groove and a second grid groove are formed in the first matrix layer and the second matrix layer, respectively, and the first grid groove and the second grid groove are filled with conductive materials, to form the first conductive layer and the second conductive layer, respectively. Accordingly, the first matrix layer and the second matrix layer may provide protection for the first conductive layer and the second conductive layer, and thus can improve the production yield. Furthermore, the present invention also provides a method for manufacturing the conductive film and a touch screen including the conductive film.

Abstract: The present invention provides a conductive film that includes a substrate, a first matrix layer, a first conductive layer, a second matrix layer, a second conductive layer, a light-shielding layer, a first lead electrode and a second lead electrode. A first grid groove and a second grid groove are formed in the first matrix layer and the second matrix layer, respectively, and the first grid groove and the second grid groove are filled with conductive materials, to form the first conductive layer and the second conductive layer, respectively. Accordingly, the first matrix layer and the second matrix layer may provide protection for the first conductive layer and the second conductive layer, and thus can improve the production yield. Furthermore, the present invention also provides a method for making the conductive film and a touch screen including the conductive film.

Abstract: A circuit board, onto which an electronic component is to be mounted, is provided with insulating core substrates and patterned metal plates. The metal plates are bonded to at least one side of the insulating core substrates. The insulating core substrates and the metal plates form a laminated body, in which a gas-vent hole is provided. The gas-vent hole is formed so that when the electronic component is mounted, the gas present between the insulating core substrates and the metal plates expands and is released to a side open to the atmosphere via the gas-vent hole.

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract: A wiring board or an electronic component embedded substrate includes a substrate that includes a resin containing a plurality of fillers; and a via that is electrically connected to at least one interconnect provided to the substrate, wherein the via includes a mix area in which metal is provided between the fillers on an inner radial side with respect to the substrate. A method of manufacturing a wiring board or an electronic component embedded substrate includes preparing a substrate that includes a resin containing a plurality of fillers; forming a via formation hole in the substrate; performing an ashing process on at least an inner wall of the via formation hole; and performing electroless plating an the inner wall of the via formation hole.

Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having circuits on one surface of the first insulating layer, a second conductor layer having circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes formed in openings of the first and second insulating layers and made of conductive materials filling the openings such that circuits in the first and third conductor layers are connected to one or more circuits in the second conductor layer, and the first and second via holes have bottom ends facing the second conductor layer and top ends larger than the bottom ends.

Abstract: Disclosed herein are a package substrate and a fabricating method thereof. The package substrate includes a substrate including at least one conductive pad, an insulation layer formed on the substrate and including an opening through which the conductive pad is exposed, a blister prevention layer formed along a top surface of the conductive pad exposed through the opening and a sidewall of the insulation layer, a metal post made of at least one alloy material and formed on the blister prevention layer, and a heat-diffusion prevention film formed on the metal post.

Abstract: Invention z-axis interconnection structures provide a means to mechanically and electrically interconnect layers of metallization in electronic substrates reliably and in any configuration. Invention z-axis interconnection structures comprise a novel bonding film and conductive paste and one- and two-piece building block structures formed therefrom.

Abstract: A wiring board according to an embodiment includes an inorganic insulating layer provided with a via-hole which is a penetrating hole, and a via-conductor which is a penetrating conductor disposed inside the via-hole. The inorganic insulating layer includes first inorganic insulating particles connected to each other and second inorganic insulating particles that are larger in particle size than the first inorganic insulating particles and are connected to each other via the first inorganic insulating particles, and also has, at an inner wall of the via-hole V, a protrusion including at least part of the second inorganic insulating particle. The protrusion is covered with the via-conductor.

Abstract: An insulating layer is formed on a support substrate having a conductive property. Write wiring traces, read wiring traces, and first and second electrode pad pairs are formed on the insulating layer. The first electrode pad pair is connected to the write wiring traces. The second electrode pad pair is connected to the read wiring traces. Parts of regions of the support substrate, which overlap the electrode pads, are removed. Thus, openings are formed in the regions of the support substrate, which overlap the electrode pads.

Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract: A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

Abstract: A wiring board includes a first substrate portion including a first feed-through conductor portion in a vertical direction, a second substrate portion provided on the first substrate portion and including a second feed-through conductor portion in a vertical direction of a corresponding part to the first feed-through conductor portion, and a feed-through electrode including the first feed-through conductor portion and the second feed-through conductor portion.

Abstract: Embodiments of the present application relate to the technical field of a printed circuit plate, in particular, to a printed circuit plate and a method manufacturing same so as to resolve a problem of an incomplete elimination of a short-line effect. The method for manufacturing a printed circuit board in the embodiments of the present application comprises a step of drilling target prepregs at positions corresponding to at least one preset hole therein so as to form through holes perforating through the target prepregs, wherein the formed through holes have an aperture greater than that of the preset hole, and the preset hole does not need to transmit electrical signal between layers of the PCB.

Abstract: A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

Abstract: A method for manufacturing a printed wiring board includes preparing a metal sheet having metal members and connectors joining the metal members, forming a structure having core substrates which are connected through the connectors and which have insulation structure portions covering the metal members, respectively, cutting the connectors in the structure such that an independent core substrate having a recessed portion is formed and a respective one of the connectors is removed from the independent core substrate, and covering the recess portion of the independent core substrate with a resin. The covering of the recess portion includes either forming an interlayer insulation layer on a surface of the independent core substrate or forming interlayer insulation layers on opposing surfaces of the independent core substrate.

Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.

Abstract: A wiring substrate includes an inorganic substrate including a substrate body formed of an inorganic material, a wiring pattern formed on the substrate body, and an external connection terminal being electrically connected to the wiring pattern, an organic substrate that is formed below the inorganic substrate, the organic substrate including an insulating layer and a wiring layer formed on the insulating layer, and a bonding layer interposed between the inorganic substrate and the organic substrate, the bonding layer including a stress buffer layer and a penetration wiring that penetrates the stress buffer layer. A thermal expansion coefficient of the stress buffer layer is greater than a thermal expansion coefficient of the inorganic substrate and less than a thermal expansion coefficient of the organic substrate. The wiring pattern and the wiring layer are electrically connected by way of the penetration wiring.

Abstract: A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.

Abstract: Disclosed herein is a method of manufacturing a printed circuit board, the method including: (a) performing a hole processing process on one surface of a core layer to process a first via hole having a predetermined height hl; (b) performing a plating process on one surface of the core layer to form a first via electrode in the first via hole and form a first metal layer on one surface of the core layer; (c) performing a hole processing process on the other surface of the core layer to process a second via hole having a predetermined height h2 exposing a lower surface of the first via electrode to the outside; and (d) performing a plating process on the other surface of the core layer to form a second via electrode in the second via hole and form a second metal layer on the other surface of the core layer.

Abstract: A wiring board includes: wiring layers; insulating layers disposed between the wiring layers; and external connection pads respectively including surface plated layers, for connecting to an external circuit. In each of the external connection pads in one face of the wiring board, an outer peripheral edge of the external connection pad is retracted from an outer peripheral edge of the surface plated layer toward a center of the external connection pad.

Abstract: An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric constant of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, and therefore reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be preformed using today's standard IC fabrication techniques.

Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface covers the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.

Abstract: A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Abstract: The present invention is an electrical connector in which a substrate (such as a printed circuit board or PCB) includes a plurality of apertures (or vias) and some of those apertures are filled with two materials to improve the characteristics of the electrical interconnection. The preferred process of crating the filled vias includes the steps of plating the vias with an electrically-conductive material to create an electrically-conductive path between portions of the substrate and components associated with the substrate and partially filling the apertures, then filling at least a portion of the apertures or vias with a second or different filling material to seal at least apart of the electrically conductive path through the plating. The second filling material may be chosen to provide thermal compensation for the connection.

Abstract: According to one embodiment, an electronic apparatus includes a housing and a flexible printed wiring board in the housing. The flexible printed wiring board includes a via, an insulator, a first conductive pattern, and a second conductive pattern. The insulator around the via includes a first surface and a second surface opposite to the first surface. The first conductive pattern is connected to the via on the first surface. The second conductive pattern is connected to the via on the second surface.

Abstract: Disclosed herein is a multilayer low temperature co-fired ceramic (LTCC) structure comprising a multilayer low temperature co-fired ceramic comprising glass-ceramic dielectric layers with screen printed thick film inner conductors on portions of the layers and with thin film outer conductors deposited on the upper and lower outer surfaces of the LTCC. At least a portion of the thin film outer conductors is patterned in the form of lines and the spacings between the lines are less then 50 ?m. Also disclosed is a process for making the LTCC structure.

Abstract: A circuit board comprises a substrate; a through hole penetrating the substrate along with a direction of a thickness thereof; and a through hole conductor covering an inner wall of the through hole. The substrate comprises a first fiber layer, a second fiber layer, and a resin layer arranged between the first fiber layer and the second fiber layer. Each of the first fiber layer and the second fiber layer has a plurality of fibers and a resin arranged among the plurality of the fibers. The resin layer contains a resin and doesn't contain a fiber. The inner wall of the through hole, in a cross-section view along with the direction of the thickness of the substrate, comprises a curved depression in the resin layer.

Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.