Abstract: A wiring board having a penetrating hole formed by forming holes with different shapes from both surfaces of a substrate. In such a penetrating hole, the depth of a first opening portion formed in the first-surface side of the substrate is shallower than the depth of a second opening portion formed in the second-surface side, and the diameter of a first opening is greater than the diameter of a second opening. Even if the gravity line of the first opening portion and the gravity line of the second opening portion are shifted from each other, the region of the second opening portion inserted into the inner space of the first opening portion may be made larger.

Abstract: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging.

Abstract: Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

Abstract: A circuit board structure with an embedded semiconductor element and a fabrication method thereof are disclosed according to the present invention. The circuit board structure comprises: a carrier board having a first surface, a second surface, and at least one through hole penetrating the carrier board from the first surface to the second surface; a first semiconductor element received in the through hole and having an active surface and an inactive surface, the active surface having a plurality of electrode pads; at least one second semiconductor element mounted on the carrier board; a first encapsulation layer formed on the first surface of the carrier board to block one end of the through hole; and a second encapsulation layer formed on the second surface of the carrier board.

Abstract: An impedance matched circuit board utilizes a series of vias, one signal via that is surrounded by four ground vias in order to effect impedance matching with a coaxial signal transmission line. The vias are plated and extend through the thickness of the circuit board. Both opposing surfaces of the circuit board are provided with a conductive ground layer and each such ground layer has an opening formed there that encompasses one or more of the vias. On the top surface the opening surrounds the signal and ground via and on the bottom surface the opening only partially surrounds the signal via and the opening includes a convex portion formed therein.

Abstract: A printed wiring board having an insulating core; a plurality of vias having axes parallel to and at equal distance from a reference axis and passing through the core; a first conductive film formed on a front surface of the core from the reference axis to each of the individual vias; a first insulating film stacked on the front surface of the core and covering the first conductive film; a first connecting via having an axis identical to the reference axis and passing through the first stacked film; a second conductive film formed on a back surface of the core from the reference axis to each of the individual vias; a second insulating film stacked on the back surface of the core and covering the second conductive film; and a second connecting via having an axis identical to the reference axis and passing through the second stacked film.

Abstract: The present invention provides a method of manufacturing printed a circuit board capable of formation of via holes having a low aspect ratio and formation of fine lines, and a printed circuit board manufactured by the method. The method of manufacturing a printed circuit board 10 according to the present invention includes a step of selectively forming a plating layer 16 for lands 22a and 22b on a metal foil 14 on the printed circuit board 10, a step of adjusting the thickness of the plating layer 16, and a step of forming the metal foil 14 into lines 14a. The aspect ratio of via holes 28 formed on lands 22a and 22b can be adjusted by adjusting the thickness of the lands 22a and 22b.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.

Abstract: A method for removing a stub of a via hole includes copperizing a wall of a via hole in a top layer of a printed circuit board (PCB) if signal lines are located on the top layer of the PCB, and a wall of the via hole in a bottom layer of the PCB is not copperized. The method further includes connecting the top layer and the bottom layer of the PCB using a connection layer.

Abstract: In one embodiment of the present invention, a connecting device of a double-sided wiring board includes a first-side connecting land portion configured by a first-side conductive layer and a first-side connecting conductive layer and a second-side connecting land portion configured by a second-side conductive layer; the first-side connecting land portion and the second-side connecting land portion face each other at respective central portions with an insulating substrate sandwiched therebetween; a substrate hole is formed corresponding to a peripheral end portion of the first-side connecting land portion and a peripheral end portion of the second-side connecting land portion; and the peripheral end portion of the first-side connecting land portion and the peripheral end portion of the second-side connecting land portion are connected to each other via the substrate hole.

Abstract: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

Abstract: A feed through for an active implantable medical device (AIMD). The feed through comprises first and second substantially planar, electrically non-conductive and fluid impermeable substrates usable for semiconductor device fabrication, each comprising: an aperture there through, and a contiguous metalized layer on the substrate surface that is co-existent with a section of the perimeter of the aperture and extends from the aperture; and a bond layer affixing the metalized layers of the first and second substrates to one another such that the apertures are not aligned with one another, and such that the metalized regions form a conductive pathway between the apertures.

Abstract: Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization.

Abstract: A connection terminal has, on an upper surface of a first dielectric layer, a first line conductor and a first grounding line conductor provided adjacent to both sides of the first line conductor, and has, on an upper surface of a third dielectric layer, a third line conductor and a third grounding line conductor provided adjacent to both sides of the third line conductor. These conductors are connected to a second line conductor and a second grounding line conductor provided adjacent to both sides of the second line conductor, respectively, the second line conductor and the second grounding line conductor being provided on an upper surface of a second dielectric layer. It is possible to obtain the connection terminal having a small size and capable of complying with a high-frequency signal.

Abstract: The invention relates to a silicon-ceramic composite substrate (01), which comprises a low-temperature ceramic (02) having at least one pre-structured ceramic layer and a silicon substrate (03). According to the invention, the low-temperature ceramic (02) forms a carrier layer and the silicon substrate surface has nanostructures (06), which are completely penetrated into the low-temperature ceramic (02), in a contact area (04) with the carrier layer.

Abstract: A substrate for an electronic circuit is provided wherein the substrate comprises a plurality of contact areas (304), a plurality of dielectric areas (307), and a conductor path (301), wherein each of the plurality of contact areas is surrounded by a respective one of the dielectric areas, and wherein at least two of the contact areas are connected with each other by the conductor path. Furthermore, the conductor path is formed at the dielectric area in such a way that it completely covers the dielectric area.

Abstract: A method for manufacturing a substrate with a metal film includes preparing a first insulation layer having first and second surfaces, forming a first conductive circuit on the first surface of the first insulation layer, forming on the first surface of the first insulation layer and on the first conductive circuit a second insulation layer having first and second surfaces, forming in the second insulation layer a penetrating hole tapering from the first surface toward the first conductive circuit, forming on the inner wall of the penetrating hole, a composition containing a polymerization initiator and a polymerizable compound, providing a polymer on the inner wall of the penetrating hole by irradiating the composition, applying a plating catalyst on the polymer, and forming a plated-metal film on the inner wall of the penetrating hole. The first surface of the first insulation layer faces the second surface of the second insulation layer.

Abstract: Various aspects provide for structures and devices to protect against spurious electrical events (e.g., electrostatic discharge). Some embodiments incorporate a voltage switchable dielectric material (VSDM) bridging a gap between two conductive pads. Normally insulating, the VSDM may conduct current from one pad to the other during a spurious electrical event (e.g., shunting current to ground). Some aspects include gaps having a gap width that is greater than 50% of a spacing between electrical leads connected to the pads. Some devices include single layers of VSDM. Some devices include multiple layers of VSDM. Various devices may be designed to increase a ratio of active volume (of VSDM) to inactive volume.

Abstract: A printed circuit board (PCB) includes a power layer, a ground layer, a through hole, and a conductor. The through hole goes through the power layer and the ground layer. The conductor includes a hollow columnar main body and an extending portion. The main body is formed in a bounding wall of the through hole, and is conductively connected to one of the power layer and the ground layer, and insulated from the other one of the power layer and the ground layer by an insulation area. The extending portion extends out from the circumferential surface of the main body. The extending portion extends into the insulation area and is insulated from the other one of the power layer and the ground layer, to increase an area of the power layer facing the ground layer.

Abstract: A circuit board (1) has a top face (2) for positioning an electronic component and a bottom face (4) used as a support on a heat-dissipating base. A plurality of heat transfer holes (12) provide heat transfer from the top face (2) to the bottom face (4). The heat transfer holes (12) are unevenly or non-uniformly distributed on the top face (2) in such a way that the top face (2) is provided with several free sectors (14) which are free of heat transfer holes (12) in order to connect the electronic component to the circuit board (1). The free sectors (14) are configured as columns or lines. A plurality of heat transfer holes (12) are placed at least along the long sides of the free sectors (14). The circuit board has a low thermal resistance between the electronic component and the heat-dissipating base.

Abstract: Disclosed herein are a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The printed circuit board includes an insulating material; a via-hole formed in a given location of the insulating material; a copper seed layer formed through ion beam surface treatment and vacuum deposition on the surface of the insulating material having the via-hole formed therein; and a copper pattern plating layer formed on a given region of the insulating material, which has the copper seed layer formed thereon, and in the via-hole.

Abstract: A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace, a second conductive signal trace, and a second conductive via disposed within the first conductive via and coupling the first conductive signal trace to the second conductive signal trace. The first conductive ground pad and the second conductive ground pad may be disposed between the first conductive signal trace and the second conductive signal trace.

Abstract: A through hole is formed in a circuit board (300) that has fibers (312) dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating (308) over the sputtered copper layer (306).

Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.

Abstract: A package for an electron element comprises: a base substrate made of ceramic; a frame body made of ceramic arranged on a top surface of the base substrate and provided therein with a cavity for accommodating the electron element; a via formed in the base substrate below the cavity, penetrating the base substrate from the top surface to a bottom surface thereof and filled with a thermally-conductive material; and a projecting part formed on an inner wall of the via and projecting toward a center of the via. The projecting part has a length along a direction perpendicular to a penetration direction of the via not less than a thickness along the penetration direction. An electronic component comprises the package and the electron element mounted thereon. The electron element is accommodated in the cavity defined inside the frame body of the package and arranged above the via.

Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.

Abstract: A method of producing substrate 3 having feedthrough electrodes for an inkjet head, including: a step of forming grooves in the substrate 1 in the same pitch as that of the inkjet head; a step of setting conductive member 101 in the grooves; a step of adhering covering substrate 2 onto substrate 1; a step of cutting adhered substrate 1 and covering substrate 2 in a direction perpendicular to that of the grooves in a predetermined width.

Abstract: A circuit board, having improved adhesion between its via conductor and insulating layer, is provided. The circuit board includes a first wiring layer, a second wiring layer, the insulating layer, a filler, and the via conductor. The first wiring layer and the second wiring layer are electrically insulated from each other by the insulating layer. The filler which has a favorable thermal conductivity is added into the insulating layer. The via conductor establishing electrical connection between the first wiring layer and the second wiring layer is formed in a predetermined position of the insulating layer. The via conductor is in direct contact with part of the filler added into the insulating layer.

Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to one another through vias formed in each of the insulating layers. In a peripheral region of the package, reinforcing patterns are provided on the same surfaces where the corresponding wiring layers are provided, respectively. Each of the reinforcing patterns is formed of a conductive layer formed on the same surface where the corresponding one of the wiring layers is provided, and is provided in an intermittent ring-like shape when viewed in a planar view.

Abstract: A structure with a multilayer plated through hole is disclosed. At least one dielectric layer formed by deposition and a conductive layer are formed in an original plated through hole (PTH). The dielectric layer partially covers wiring layers of the substrate to electrically isolate the PTH and the conductive layer to form a multilayer PTH so as to save PTH occupation space of the substrate. Preferably, the formation of the dielectric layer is electrophoretic deposition to control the deposition thickness in the PTH very even and thin, no drilling is necessary. Accordingly, it can increase electrical performance and decrease cross-talk effect.

Abstract: A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture pad, a focused laser beam is moved linearly to form linear channels in the dielectric layer. These channels are filled with an electrically conductive material to form the capture pad.

Abstract: A printed wiring board includes a resin insulation layer having a first surface and a second surface on an opposite side of the first surface, the resin insulation layer having an opening for a first via conductor, a pad formed on the first surface of the resin insulation layer and provided to mount an electronic component, a first conductive circuit formed on the second surface of the resin insulation layer, and a first via conductor formed in the opening and connecting the pad and the first conductive circuit. The pad has an embedded portion embedded in the resin insulation layer and a protruding portion protruding from the resin insulation layer, and the embedded portion has an external shape which is greater than an external shape the protruding portion.

Abstract: Wiring board bases 2 to 4 are provided with: insulating substrates 1a to 4a having conductive layers 1b to 4b provided on one surfaces thereof, respectively; through-holes 2e to 4e which are arranged on the insulating substrates and reach the conductive layers from the other surfaces; and conductive vias 2d to 4d connected to the conductive layers by filling the through-holes with a conductive paste. In a method for manufacturing a laminated wiring board, at least one of the wiring board bases is stacked. Before the through-hole is filled with the conductive paste, a surface portion, in the through-hole, of the conductive layer is smoothed and a smooth surface portion 2g is formed.

Abstract: A circuit board includes: a plurality of wiring layers; an insulating layer which insulates the plurality of wiring layers, the insulating layer containing a fibrous filler and a resin; and a conductor part formed on a sidewall of a via piercing through the insulating layer. The fibrous filler protrudes from the sidewall and is covered with the conductor part, with a length greater than the thickness of the conductor layer.

Abstract: Disclosed is a printed circuit board having a plating pattern buried in a via and a method of manufacturing the same. The method of manufacturing the printed circuit board includes forming a negative pattern for forming a plating pattern, thus remarkably reducing the generation of plating thickness deviation in a plating process for forming a circuit pattern, and the printed circuit board has improved electrical signal transmission properties.

Abstract: Disclosed herein is a printed circuit board, including: metal bumps having constant diameters and protruding over an insulation layer; a circuit layer formed beneath the insulation layer; and vias passing through the insulation layer to connect the metal bumps with the circuit layer.

Abstract: A multilayer ceramic substrate includes a plurality of ceramic layers laminated each other. The plurality of ceramic layers form a bulge and a cavity having such a shape that an opening area of the cavity gradually becomes smaller toward a bottom of the cavity.

Abstract: The invention relates to a printed circuit board having metal bumps which are of even heights and are directly connected to a circuit pattern without using additional bump pads thus allowing an arrangement thereof at fine pitches.

Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as strength and thermal expansion coefficient. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs formed by disposing carbon fibers so as to produce openings at positions where plated through holes will pass through and impregnating the carbon fibers with resin; a step of forming through holes that pass inside the openings at positions of the openings in the core portion; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the carbon fibers and thereby produce a core substrate.

Abstract: Printed circuit board capacitors include a first electrode comprising a via extending at least partially through a multi-layer printed circuit board and a plurality of conductive pads in electrical contact with the via and extending radially outward from the via, and a second electrode electrically isolated from the first electrode and comprising a plurality of ground-plane layers of the printed circuit board. The plurality of ground-plane layers include electrically conductive material overlapping the plurality of conductive pads.

Abstract: A plurality of vias is disposed side by side on a multilayer board. A first via which is one of the vias disposed at one outer portion is electrically connected to a first outgoing line provided on the multilayer board. A second via at the other outer portion is electrically connected to a second outgoing line provided on the multilayer board. A plurality of the vias is connected to a first fixed potential layer (a ground layer, for example) of the multilayer board. At least one second fixed potential layer is provided, with a plurality of the vias through a clearance and having the same potential as that of the first fixed potential layer, as an inner layer of the multilayer board between the first and second outgoing lines and the fixed potential layer. Therefore, a BPF whose rate of occupied area is low is formed on the multilayer board without additional production processes.

Abstract: A multilayered board data input unit inputs design data of a multilayered circuit board provided with through holes penetrating and mutually connecting solid-layer conductors disposed in a multilayer manner. A limitation rule setting unit sets a limitation rule for limiting the number of solid-layer conductors to be connected to the through holes. A separation processing unit separates connections of the solid-layer conductors to the through holes in the design data based on the limitation rule. At this time, when a solid-layer conductor to be separated from the through holes is selected as a candidate, the separation processing unit determines whether the solid-layer conductor is isolated by separation, when the solid-layer conductor is not isolated, determines isolation, and when the solid-layer conductor is isolated, stops separation.

Abstract: A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.

Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.

Abstract: Methods for controlling thermal conductivity paths in a metal core circuit board, as well as methods to provide selective electrical isolation, are described. In one embodiment, grooves are formed in an aluminum substrate surrounding areas where electrical components are to be mounted on the substrate. The grooves are oxidized along with the opposing surface of the substrate to create a vertical oxide ring around the area for electrical and lateral thermal isolation. This also allows the substrate to be made relatively thick for mechanical strength. Other features include forming copper around oxidized sides of the substrate for connection between top and bottom copper layers; plating up copper to be co-planar with a raised dielectric layer; forming indentions in the substrate for containing a dielectric so the dielectric is co-planar with the remaining surface; forming copper vias through the substrate; and planarizing the substrate surface so that conductors and dielectric layers are co-planar.

Abstract: An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.

Abstract: A method for forming a via in a printed circuit board is disclosed, which via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal planes. The method comprises forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.

Abstract: Provided is a method of manufacturing a ceramic multi-layer circuit substrate. A plurality of ceramic blocks, in each of which one or more ceramic green sheets having via-electrodes are layered one atop the other, are formed and are then fired. The fired ceramic blocks are aligned with each other. One or more bonding green sheets each having bonding electrodes in positions corresponding to the via-electrodes of the ceramic blocks are prepared. Each of the bonding green sheets is interposed between a pair of the ceramic blocks opposing each other. The ceramic blocks and the bonding green sheets are bonded and are then fired.