Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

Abstract: A lower sub-board of a circuit board includes a first base layer having an upper surface, and a first wiring pattern provided on the upper surface of the first base layer. An upper sub-board of a circuit board includes a second base layer having a lower surface, and a second wiring pattern provided on the lower surface of the second base layer. A connection layer between lower and upper sub-boards includes an insulating layer having a lower surface and an upper surface, the lower surface of connection layer being situated on the upper surface of the first base layer, the upper surface of connection layer being situated on the lower surface of the second base layer, and a via-conductor passing through the insulating layer and connected to the first and second wiring patterns. This circuit board connects the sub-boards to each other via a via-conductor densely.

Abstract: An enhanced mechanism is disclosed for via stub elimination in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first and second ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first and second conductive vias are respectively plated onto the first and second through-holes. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the first and second conductive vias from extending substantially beyond the first and second internal conductive traces, respectively, and thereby prevent via stubs from being formed in the first place.

Abstract: A mechanism is disclosed for providing horizontally split vias are provided in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first/second ones and third/fourth ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first/second conductive vias are plated onto the first through-hole and before third/fourth conductive vias are plated onto the second through-hole. The depth of these PTH plugs is controlled (e.g.

Abstract: The present invention discloses a flexible printed circuit (FPC) layout and a method thereof.

Abstract: Provided is a manufacturing method of a layered ceramic electronic component capable of preventing appearance of a gap between a dielectric layer and a via electrode to achieve reliable conduction between the via electrode and an internal electrode and at the same time, capable of effectively preventing occurrence of structural defects in the dielectric layer and the like. In a layered (multilayer) ceramic capacitor, dielectric layers and internal electrodes are stacked alternately. Of the internal electrodes, those placed opposite to each other via the dielectric layer are connected through the via electrode. The layered (multilayer) ceramic capacitor is produced by forming a via hole in stacked layers of a ceramic green sheet for forming the dielectric layer and a conductive paste for forming the internal electrode, followed by firing to obtain stacked layers having the dielectric layers and the internal electrodes formed therein.

Abstract: The present invention relates to a printed circuit board arrangement with a multi-layer substrate (1, 2) having a buried conductor (4) and a contact area (3), connected to the conductor (4) and being disposed on a surface of the substrate. In order to improve the cooling of the buried conductor, a metal cooling area (6) is provided above the conductor (4), and is connected to the conductor by means of one or more via conductors (7).

Abstract: A printed circuit board for mounting electronic parts thereon includes a ground portion formed on the printed circuit board and connected to an outer ground. A plurality of conductive ground layers are stacked so as to interpose an insulation layer therebetween. An upper conductive ground layer includes first and second conductive ground portions. The first and second ground portions are connected by a connecting element. Another conductive ground layer under the upper conductive ground layer is grounded via the first and second ground portions of the upper conductive ground layer via a through hole provided in the ground portion.

Abstract: A method for manufacturing a ceramic substrate having a via hole(s) and a surface wiring pattern electrically connected to the via hole(s). The method includes: preparing a sintered ceramic substrate having a via hole(s); forming over the sintered ceramic substrate a sintered ceramic layer having a hole(s) or opening(s) whose bottom is configured to be at least a part of an exposed end surface of the via hole(s) by post-firing method; forming inside the hole(s) or opening(s) a conductive portion which electrically connects the surface of the sintered ceramic layer and the via hole(s); and forming over the surface of the sintered ceramic layer a surface wiring pattern electrically connected to the conductive portion.

Abstract: A circuit board structure including a circuit board main body and an injection molded three-dimensional circuit device encapsulating at least a portion of the circuit board main body is provided. The three-dimensional circuit device includes a molded plastic body having a non-plate type, stereo structure, on which a three-dimensional pattern is also fabricated. The three-dimensional pattern is interconnected with a contact pad on the circuit board main body through a conductive via.

Abstract: A printed circuit board (PCB) includes a top layer, a bottom layer, and reference layers between the top layer and the bottom layer. A via defined through the top layer, reference layers, and the bottom layer has only two pads at the reference layers.

Abstract: The present invention essentially relates to a method of preparing an electrically insulating film at the surface of an electrical conductor or semiconductor substrate, such as a silicon substrate. According to the invention, this method comprises: a) bringing said surface into contact with a liquid solution comprising: a protic solvent; at least one diazonium salt; at least one monomer that is chain-polymerizable and soluble in said protic solvent; at least one acid in a sufficient quantity to stabilize said diazonium salt by adjusting the pH of said solution to a value less than 7, preferably less than 2.5; b) the polarization of said surface according to a potentio- or galvano-pulsed mode for a duration sufficient to form a film having a thickness of at least 60 nanometres, and preferably between 80 and 500 nanometres. Application: Metallization of through-vias, especially of 3D integrated circuits.

Abstract: A multiwall via structure in an electronic substrate having multiple conductive layers. The multiwall via structure includes an outer via coupled to a pair of the conductive layers, an inner via within the outer via and coupled to the same pair of conductive layers, and a dielectric layer between the inner and outer vias. In various embodiments, the pair of conductive layers can be inner conductive layers or outer conductive layers of the electronic substrate. In other embodiments, a method of preparing a multiwall via structure is provided.

Abstract: A printed circuit board includes a through hole constituted by a hole penetrating through the front and rear surfaces of the printed circuit board. A fabrication method of the printed circuit board, includes applying conductive material plating to the inner wall surface of the hole to form a through hole electrically connecting the front and rear surfaces of the printed circuit board, and removing the conductive material plated on the hole inner wall surface at least at a portion between the front and rear surfaces of the printed circuit board is carried out to thereby fabricate a printed circuit board having a through hole electrically isolates the front surface of the printed circuit board from the rear surface thereof.

Abstract: A printed circuit board includes a first layout layer, a second layout layer, a copper foil layer, a first via and a second via. The first layout layer has a first signal line and a second signal line, each of which has a curved first portion. The second layout layer has a third signal line and a fourth signal line, each of which also has a curved first portion. The curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line are coupled to the first via and the second via. In this case, the curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line cooperatively generate spiral inductance characteristic.

Abstract: First, a plurality of wiring boards are fabricated at separate steps. The first wiring board includes a Cu post formed on a wiring layer on one surface of a substrate, and a first stopper layer formed at a desired position around the Cu post. The second wiring board includes a through hole for insertion of the Cu post therethrough, a connection terminal formed on a wiring layer on one surface of a substrate, and a second stopper layer that engages the first stopper layer and functions to suppress in-plane misalignment. The third wiring board includes a connection terminal formed on a wiring layer on one surface of a substrate. Then, the wiring boards are stacked up, as aligned with one another so that the wiring layers are interconnected via the Cu post and the connection terminals, to thereby electrically connect the wiring boards. Thereafter, resin is filled into gaps between the wiring boards.

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract: This document discusses, among other things, a method including providing a laminate having a first conductive layer, a second conductive layer and an insulator between the first and second conductive layers. A hollow conductive via is formed through the insulator, the conductive via electrically connects the first and second conductive layers. At least one conductive trace electrically connects the hollow conductive via to at least one of the first and second conductive layers. The method further includes forming a channel in the insulator adjacent to the hollow conductive via and the channel surrounds the via. Wherein the channel extends at least part way between the first and second conductive layers, the at least one conductive trace bridges the channel, and the via is isolated from the insulator by the surrounding channel formed adjacent to the hollow conductive via.

Abstract: Provided is a method of manufacturing a PCB, the method comprising: providing a substrate including an aluminum core; forming a via hole passing through the substrate; substituting the surface of the aluminum core with a zinc film by performing a zincate treatment on the inner surface of the via hole; substituting the zinc film with a metal film by performing substitution plating on the zinc film; forming a first plated film on the surface of the via hole, where the metal film is formed, through electroless plating; and forming a second plated film on the first plated film through electroplating.

Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.

Abstract: A printed circuit board with ground grid includes a first insulating plate, a plurality of first metal lines formed on the first insulating plate, a sub-circuit board above the plurality of first metal lines, a second insulating plate above the sub-circuit board, a plurality of second metal lines formed on the second insulating plate, and, a plurality of conductive components formed in and through the second insulating plate and the sub-circuit board to electrically connect the plurality of first metal lines and the plurality of second metal lines. As additional electronic elements and circuits can be located on the first insulating plate and/or on the second insulating plate without limitation, difficulties for printed circuit board layout can be dramatically reduced.

Abstract: A multilayer ceramic substrate in which an active element and a passive element are surface-equipped over the outermost surface on one side is provided. The multilayer ceramic substrate comprises a plurality of laminated ceramic substrate layers, a surface layer terminal electrode provided in a via hole of an outermost ceramic substrate layer on at least one side and having a surface layer via electrode and a metal plating layer deposited over an end surface of the surface layer via electrode, and a via conductor which connects the surface layer terminal electrode and circuit patterns over the ceramic substrate layer at the inside, wherein a via hole size of a surface layer terminal electrode for connection of the active element is smaller than a via hole size of a surface layer terminal electrode for connection of the passive element.

Abstract: An object of the present invention is to provide a method for manufacturing a porous material in which complicated and fine through portions, recessed portions, and the like have been patterned. It is to provide a patterned porous molded product or nonwoven fabric, in which a plated layer has been selectively formed on the surfaces of the through portions and the recessed portions. With the invention, a mask having through portions in a pattern is placed on at least one side of the porous molded product or the nonwoven fabric. A fluid or a fluid containing abrasive grains is sprayed from above the mask, thereby to form through portions or recessed portions, or both of them, to which the opening shape of each through portion of the mask has been transferred, in the porous molded product or the nonwoven fabric.

Abstract: A multilayer printed wiring board includes a first interlaminar resin insulating layer, a first conductor circuit formed on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer formed on the first interlaminar resin insulating layer and the first conductor circuit, a second conductor circuit formed on the second interlaminar resin insulating layer. A via conductor can be formed in the opening portion. The opening portion of the second interlaminar resin insulating layer can expose a face of the first conductor circuit. The via conductor connects the first conductor circuit and the second conductor circuit. The via conductor includes an electroless plating film formed on inner wall face of the opening portion and includes an electrolytic plating film formed on the electroless plating film and on the exposed face of the first conductor circuit exposed by the opening portion.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating coats a surface of the dielectric layer in the first opening. An electrically insulating material substantially fills the first opening. The circuit board includes a first additional dielectric layer attached to the first planar surface, and a second additional dielectric layer attached to the second planar surface. A second opening extends through the first additional dielectric layer, the electrically insulating material filling the first opening, and the second additional dielectric layer.

Abstract: First, a structure is fabricated by directly bonding a first base material and a second base material. The first base material has a recessed portion formed in a desired patterning layout on one surface thereof, and the bonding is performed in such a manner that the surface having the recessed portion of the first base material faces inward. Then, through holes are formed at desired positions in the structure in such a manner that the through holes pierce the structure in a direction of thickness thereof and communicate with the corresponding recessed portions. Further, an insulating layer is formed on the surface of the structure, and thereafter, a conductive material is filled into the through holes and the recessed portions.

Abstract: An apparatus comprising a printed circuit board having a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels; a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel; and an impedance matching terminal electrically coupled to the stub and to a ground. A process comprising providing a printed circuit board including a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels, and a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel and being designed to receive a signal from a component attached to the printed circuit board; and coupling an impedance matching terminal to the stub and to a ground.

Abstract: Through hole (3) for product, through holes (7a, 7b) for laminate recognition marks, through holes (8a, 8b) for an X-ray recognition marks are formed on prepreg sheet (1) having mold release films (2a, 2b) attached to the front and back surfaces thereof. By masking through holes (7a, 7b) for laminate recognition mark, conductive paste (4) is filled in through hole (3) for product and through holes (8a, 8b) for X-ray recognition marks. Thereafter, mold release films (2a, 2b) are removed so as to manufacture a circuit board. Since conductive paste (4) is not filled in through holes (7a, 7b) for laminate recognition marks, a recognition mark with high laminating accuracy can be easily obtained, and a high density and high quality circuit formation substrate having improved laminating accuracy can be obtained.

Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The method in accordance with an embodiment of the present invention includes: providing a substrate on which a first insulation layer, a first circuit pattern, a second insulation layer and a resin layer are successively laminated; boring a through-hole penetrating the substrate; forming roughness on the resin layer by a desmear process; forming a via making an electrical connection between layers through the through-hole; and forming a second circuit pattern on the resin layer having roughness formed thereon.

Abstract: A printed circuit board for preventing electrostatic discharge damage includes several electronic components thereon. The printed circuit board defines a number of through holes therein. The printed circuit board includes a signal layer. The signal layer defines a first copper foil and second copper foil thereon. The first copper foils are disposed around the corresponding through holes and connect with the through holes. The second copper foils are disposed around the first copper foils and extend to two adjacent edges of the printed circuit board. The first copper foil and the second copper foil have a number of saw teeth. A gap between the first copper foil and the second foil is in the range from 0.1-0.125 mm.

Abstract: Closed vias are formed in a multilayer printed circuit board by laminating a dielectric layer to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer.

Abstract: A multilayer wiring board is manufactured by preparing a first wiring board, a second wiring board, and a joint sheet. The first wiring board is provided with a via having a first through-hole in which a conductive film is formed. The second wiring board is provided with a second through-hole at a position substantially matching the position of the first through-hole. The joint sheet is provided with a third through-hole at a position substantially matching the positions of the first and the second through-holes. the first wiring board and the second wiring board are stacked and bonded together by heat and pressure with the joint sheet interposed therebetween.

Abstract: Embodiments of the invention include a Printed Wiring Board (PWB) having a first via connected to a top-side signal source, a second via connected to a bottom-side signal destination, and a third via connected to the first via on a lower signal layer of the PWB and further connected to the second via on an upper signal layer of the PWB. In embodiments of the invention, the third via is referred to as an S-Turn via. The S-Turn PWB routing configuration advantageously reduces reflections causes by via stubs at Multi-Giga Hertz (MGH) frequencies. Other embodiments are described.

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract: A protection circuit assembly and a battery pack including the same, which can simplify a manufacturing process and increase productivity. The protection circuit assembly includes a protection circuit board including a connection terminal, and a first lead plate connected to the connection terminal and having a coupling hole. The battery pack includes a bare cell having a protrusion, and a protection circuit assembly electrically connected with the bare cell and including a first lead plate having a coupling hole. Accordingly, the battery pack includes a protection circuit assembly including a lead plate having a coupling hole, and a bare cell including a structure inserted into the coupling hole, and thus it is possible to simplify a manufacturing process and increase productivity.

Abstract: A multilayer printed wiring board is characterized in that the interlayer connection material in the via holes has a lower coefficient of thermal expansion in the thickness direction than the electrically insulating substrate made of insulating material; the interlayer connection is formed at a temperature higher than the operating temperature; and the interlayer connection material is larger in thickness than the interlayer connection material of the same wiring layer at normal temperature. This causes a difference in the coefficient of thermal expansion between the different materials in the thickness direction of the printed wiring board in the environment in which it is used resulting in high connection reliability.

Abstract: A printed wiring board having a through hole conductor formed on the surface of a through hole formed in a copper-clad laminate board, and on the surface of the copper-clad laminate board 1 in the vicinity of an opening of the through hole. The through hole conductor is filled with a positive photosensitive resin. A capped conductor is formed on the positive photosensitive resin and is coupled to the through hole conductor. Further, a circuit pattern is formed on the surface of the copper-clad laminate board. An insulating layer is formed on the surface of the copper-clad laminate board, capped conductor, and the circuit pattern, and formed with a via hole extending from the surface of the insulating layer to the capped conductor. A via conductor is formed inside the via hole and on the surface of the insulating layer in the vicinity of an opening of the via hole.

Abstract: A printed circuit board and a manufacturing method of the same. The method includes forming a circuit board by selectively positioning a heat release layer among multiple insulation layers that have circuit patterns formed on their surfaces, perforating a through-hole that penetrates through one side and the other side of the circuit board, forming a metal film over the heat release layer exposed at an inner wall surface of the through-hole, and forming a plating layer by depositing a conductive metal over an inner wall of the through-hole. By having the heat release layer selectively inserted inside the circuit board, the heat releasing effect may be improved, and the bending strength may be increased. Moreover, a reliable electrical connection can be implemented between the heat release layer and the circuit pattern, making it possible to utilize the heat release layer as a power supply layer or a ground layer.

Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract: A multilayer printed circuit board has an insulation layer, a first conductor layer provided over a first side of the insulation layer, a second conductor layer provided over a second side of the insulation layer opposite to the first side, and multiple filled vias electrically connecting the first conductor layer and the second conductor layer. The filled vias have upper surfaces, respectively, and each of the upper surfaces is made such that a difference between a lowest point and a highest point of each of the upper surfaces is less than or equal to about 7 ?m.

Abstract: A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as the thermal expansion coefficient of the circuit board. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs which include first fibers that conduct electricity and second fibers that do not conduct electricity, which have the second fibers disposed at positions where plated through holes will pass through, and which are impregnated with resin; a step of forming through holes at positions in the core portion where the second fibers are disposed; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the first fibers and thereby produce a core substrate.

Abstract: There is provided a wiring substrate. The wiring substrate includes: a core substrate formed of a conductive material and having a through hole therein; an insulating layer formed on first and second surfaces of the core substrate; wiring patterns formed on the first and second surfaces via the insulating layer; and a via formed in the through hole and electrically connected to the wiring patterns. The via includes: a conductor ball and a conductor portion. The conductor ball has a conductive surface and an insulating member covering the conductive surface. A portion of the conductive surface is exposed from the insulating member. The conductor portion is electrically connected to the exposed conductive surface and the wiring patterns. At least one of the insulating member and the insulating layer is interposed between the via and the core substrate.

Abstract: An electrically conductive shock mount system for electrical subassemblies is provided. The shock mount system includes a first assembly having a housing containing a hook member for a hook and loop fastener. The second assembly has a housing containing a loop member for a hook and loop fastener. A plurality of holes in the housings of the first and second assemblies allows the hook member to engage the loop member. In one embodiment, the housings are made from a conductive fabric and include a plurality of conductive columns that extend through the housings.

Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.

Abstract: A method is provided for manufacturing a multilayer substrate. An insulating layer can have a hole overlying a patterned second metal layer. In turn, the second metal layer can overlie a first metal layer. A third metal layer can be electroplated onto the patterned second metal layer within the hole, the third metal layer extending from the second metal layer onto a wall of the hole. When plating the third metal layer, the first and second metal layers can function as a conductive commoning element.

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

Abstract: In order to suppress the occurrence of damage on a press-fit joining wiring board, a peak value of stress generated on the board in the case of a press-fitting a press-fit terminal into a through-hole is reduced so that it can not exceed the design standard value of the board. In the press-fit terminal in which a body part, retaining part, introducing part and forward end part are integrally formed, a cross-sectional area of the introducing part is reduced to be smaller than that of the retaining part, so that an intensity of the elastic force of the introducing part is decreased to be lower than that of the elastic force of the retaining part. Alternatively, on the wiring board, elastic material is filled into resin for combining sheet-like base material of the board so as to relieve an intensity of stress generated on the board itself.

Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.

Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.