Abstract: A process for fabricating a circuit board is provided. A circuit substrate having a first surface and a first circuit layer is provided. A first dielectric layer having a second surface is formed on the circuit substrate and covers the first surface and the first circuit layer. An antagonistic activation layer is formed on the second surface. The antagonistic activation layer is irradiated by a laser beam to form at least a blind via extended from the antagonistic activation layer to the first circuit layer and an intaglio pattern. A first conductive layer is formed inside the blind via. A second conductive layer is formed in the intaglio pattern and the blind via. The second conductive layer covers the first conductive layer and is electrically connected with the first circuit layer through the first conductive layer. The antagonistic activation layer is removed to expose the second surface.

Abstract: A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.

Abstract: Disclosed are a carrier substrate including an insulating base material with a copper foil layer formed on at least one surface thereof, a metal layer formed on the cooper layer and having a length shorter than that of the copper foil layer, and an insulating layer formed on the metal layer, a fabrication method thereof, a printed circuit board (PCB) using the same, and a fabrication method thereof. Because there is no land at the via and core in the substrate, because a circuit pattern connected with the via can be formed to be finer, so the circuit pattern can be highly integrated and the substrate can become thinner. Thus, a printed circuit board (PCB) having a smaller size and reduced number of layers can be fabricated.

Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract: There are provided a multilayer ceramic substrate and a probe board formed using a pillar-type conductor formed by including preparing a ceramic sheet having at least one through hole; filling the inside of the through hole with a conductive material; firing the ceramic sheet so that the conductive material is fired to form a pillar-type conductor; and removing the ceramic sheet so that the pillar-type conductor remains, and fabricating methods of the same. The multilayer ceramic substrate and the probe board use the pillar-type conductor that can fill the unfilled region formed within the ceramic sintered body, such that the electrical characteristics and surface flatness thereof are improved. In addition, the multilayer ceramic substrate and the probe board formed by using the pillar-type conductor with the improved adhesion and electrical characteristics between the ceramic sintered body and the connecting pad, and the fabricating methods of the same are provided.

Abstract: A printed circuit board having at least two spaced apart conductive planes. A plurality of vias extend between the two spaced apart conductive planes with the vias being electrically connected to a selected one of the two conductive planes in an alternating pattern. A differential electrical signal is connectable to the conductive planes so that the vias are alternately energized by the differential electrical signal when the differential electrical signal is connected to the conductive planes.

Abstract: The present invention provides a printed circuit board assembly that includes a first printed circuit board portion having a first thickness and including at least one plated through hole selectively electrically interconnecting electrically conductive layers of the printed circuit board assembly. A second printed circuit board portion is also provided that has a second thickness which is less than the first thickness and further includes another a second plated through hole array exposed on a surface of the second printed circuit board portion.

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Abstract: An electrical connector assembly includes a circuit board having vias extending at least partially through the circuit board along via axes. The circuit board has traces and mounting pads that are electrically connected to corresponding traces, and that are exposed within corresponding vias. The vias have a staged diameter along the via axis with a constricted region proximate to the mounting. An electrical connector is mounted on the circuit board. The electrical connector includes a housing and signal terminals held by the housing. The signal terminals include mounting contacts being received in respective vias of the circuit board that engage corresponding mounting pads in the constricted region.

Abstract: A method for manufacturing a multilayer printed circuit board, and a printed circuit board manufactured according to the method, includes laterally-aligning a first inner substrate in which first insulation layers and first conductor layers are alternately laminated and a second inner substrate in which second insulation layers and second conductor layers are alternately laminated. The second inner substrate has a lager number of layers than the first inner substrate. The laterally-aligned first inner substrate and second inner substrate are placed between a pair of third insulation layers in a thickness direction. The pair of the third insulation layer are heated under pressure in the thickness direction. A conductor pattern is formed on surfaces of the pair of the third insulation layers.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate with vias extending between first and second surfaces thereof, and at least one helical inductor adapted within a via, which may be formed of a conductive material. Other embodiments are described and claimed.

Abstract: A printed circuit board manufacturing method includes: a hole-forming step of forming a through hole in a substrate that will become an element of a printed circuit board after manufacturing; and a jig insertion step of inserting a jig in the through hole formed in the hole-forming step such that the jig adheres to a portion of an inner wall of the through hole, the inner wall having a portion connecting to the outside of the through hole. The method further includes a conductive-film forming step of forming a conductive film only on the portion of the inner wall of the through hole connecting to the outside of the through hole, after the jig is inserted into the through hole in the jig insertion step.

Abstract: A method and apparatus for filling a via with transparent material is presented, including the steps of providing a panel having a via, occluding the via with transparent material in a workable state so that a portion of the occluding material is internal to the via and a portion of the material is external to said via. The external and internal portions are separated so the transparent filler material, when set, forms a smooth and featureless surface. This causes the filled via to have a substantially even and uniform appearance over a wide range of viewing angles when lit.

Abstract: A packaged structure having a magnetic component and a method of manufacturing the same are provided. The packaged structure includes an insulating substrate having a ring-typed recess, an island portion and a surrounding portion defined by the ring-typed recess, wherein the ring-typed recess is laterally between the island portion and the surrounding portion.

Abstract: A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor element sealed substrate. Next, the semiconductor element sealed substrate and the wiring substrate are stacked on each other in such a way that electrode terminals of the semiconductor element and corresponding conductive bumps on the outermost wiring layer face each other. The electrode terminals and the conductive bumps are thus connected to each other.

Abstract: Disclosed herein is a method of manufacturing a printed circuit board, including: forming a buildup layer on a base substrate including a circuit layer connected with a first via penetrating an insulation layer; forming a viahole penetrating the buildup layer and at least a part of the first via; and forming an interlayer connection member in the viahole. The method is advantageous in that a process of forming a multilayer connection structure can be simplified, and an error in the formation of a viahole can be minimized.

Abstract: A printed circuit board includes a substrate including a first surface and a second surface opposite to the first surface, a pair of first pads positioned on the first surface and the second surface, and a plurality of insulating areas. The substrate defines a through hole and a plurality of vias extending from the first surface to the second surface. Each of the pair of first pads surrounds the through hole. The insulating areas are adjacent to the first pad to divide a reference metal layer of the substrate adjacent to the first pads into a plurality of metal strips to reduce heat dissipation area of the reference metal layer adjacent to the first pads. The vias are adjacent to the metal strips to supply extra heat to molten solder on the first surface in a wave-soldering process.

Abstract: The invention relates to a method for making a connection component that comprises a set of conducting inserts to be electrically connected with another component, said inserts being hollow.

Abstract: Provided are a multi-layer interconnection structure and a manufacturing method thereof. The multi-layer interconnection structure includes a substrate; a first wiring on the substrate; an interlayer insulation layer on the first wiring; a second wiring on the interlayer insulation layer; and a via contact including at least one conductive filament penetrating through the interlayer insulation layer between the second wiring and the first wiring to be electrically connected to the first wiring and the second wiring.

Abstract: Disclosed are a printed circuit board including a core substrate including core circuit layers on both sides thereof, a first build-up layer formed on one side of the core substrate, a second build-up layer formed on the other side of the core substrate, and first and second protective layers formed on the first and second build-up layers, respectively, wherein the first build-up layer includes a trench circuit layer as an outermost circuit layer formed by a trench-forming technology, and the trench circuit layer is embedded in the first protective layer, and a method of manufacturing the printed circuit board. Thanks to the formation of the outermost circuit layer by the trench-forming technology, it is difficult to separate the outermost circuit layer from the outermost insulating layer.

Abstract: The present disclosure relates to a conductive structure. The conductive structure includes a first conductive layer, a conductive unit, a circuit board and a conductive material. The conductive unit is disposed on the first conductive layer. The circuit board having a first through hole is disposed on the first conductive layer. The conductive unit is exposed to the first through hole. The first through hole is filled with a conductive material, such that the conductive material is electrically connected to the conductive unit.

Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

Abstract: A three-dimensional PWB is provided that may include two or more layers stacked together forming a top surface, a bottom surface, and one or more side surfaces, and one or more solder pad situated on at least one of the one or more side surfaces. The one or more solder pads may include exposed voids in the one or more side surfaces. In some cases, the top surface and/or the bottom surface may have one or more solder pad. The one or more solder pads on at least one of the one or more side surfaces may be electrically connected to the one or more solder pads on the top surface and/or the bottom surface. In the illustrative PWB, the top surface and/or the bottom surface may be adapted to be mounted with an inertial sensor. The one or more side surfaces may be adapted to be mounted to a printed wiring board.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract: Systems and methods for providing mechanically reinforced plated through-holes (PTH) in PCBs, which advantageously allow improved soldering capabilities and reliability, are described herein. Such systems and methods are achieved by reducing the heat sinking effects of PTHs by providing one or more vias surrounding the PTHs to provide an electrical connection between the PTH and the internal and bottom conductive layers of a PCB. In this regard, the PTHs are spaced apart from at least one of the internal conductive layers (e.g., ground or power layers), so the heat sinking effects are reduced. This feature enables molten solder to substantially fill the entire PTH before freezing, thereby improving the mechanical and electrical connection between an electrical component and the PCB. One or more electrically-nonfunctional lands (or “rib reinforcements”) are provided in internal conductive layers to mechanically support the walls of the PCB.

Abstract: Provided are a printed circuit board (PCB), and a manufacturing method thereof. The PCB includes a stacked structure including second and third insulation layers with a first insulation layer interposed therebetween, and a conductive via having first to fourth conductive vias. A second-layer circuit pattern and a third-layer circuit pattern are buried in the first insulation layer, a first-layer circuit pattern is formed on the second insulation layer, and a fourth-layer circuit pattern is formed on the third insulation layer. A first conductive via connects the first-layer circuit pattern and the second-layer circuit pattern, a second conductive via connects the first-layer circuit pattern and the third-layer circuit pattern, a third conductive via connects the second-layer circuit pattern and the fourth-layer circuit pattern, and a fourth conductive via connects the third-layer circuit pattern and the fourth-layer circuit pattern.

Abstract: Provided is an electronic circuit device in which the bonding state of electrodes can be detected easily with high precision. The electronic circuit device has a stack structure in which a plurality of electronic circuit boards (1a, 1b, 100a, 100b, 100c) are stacked in three or more layers through ball electrodes (10a, 10b, 20a, 20b) bonded to electrode pads (30a, 30b, 40b, 50a, 60a), wherein the electrode pads are disposed such that transmission shaded images of a pair of the electrode pads provided between adjacent layers partially overlap each other and have a non-overlapping region in which the transmission shaded images of the pair of electrode pads are free from overlapping and such that the transmission shaded image of the non-overlapping region is at least partially free from overlapping with transmission shaded images of all the other electrode pads.

Abstract: A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.

Abstract: A submount for an electronic device includes an electrically insulating substrate including first and second surfaces and having a thickness between the first and second surfaces, a thermally conductive pad on the first surface of the substrate, and a thermally conductive via extending from the first surface of the substrate toward the second surface of the substrate and having a length that is less than the thickness of the substrate. The thermally conductive via has a higher thermal conductivity than a thermal conductivity of the substrate. Methods of forming submounts are also disclosed.

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole for a via conductor, a conductive circuit formed on one surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and having a protruding portion protruding from the other surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the protruding portion of the via conductor. The via conductor is connected to the conductive circuit and has a first conductive layer formed on the side wall of the penetrating hole and a plated layer filling the penetrating hole.

Abstract: An electrically insulating substrate is provided. The electrically insulating substrate includes a set of areas to be formed into a set of printed circuit boards. Each of the set of areas is separated from others of the set of areas by a dicing channel. A set of signal wiring conductors is fabricated onto the set of areas of the electrically insulating substrate so that at least one of the set of signal wiring conductors terminates proximate to the dicing channel. A set of plated through holes is fabricated through at least one of the set of areas such that at least one of the set of plated through holes connects to at least one of the set of signal wiring conductors. The electrically insulating substrate is singulated along a set of singulation lines to form the set of printed circuit boards. The singulation lines intersect with the plated through holes, so that a portion of the plated through holes is exposed along the peripheral edge of the resulting printed circuit boards.

Abstract: A printed wiring board includes a substrate having a first surface and a second surface on the opposite side of the first surface and multiple first penetrating holes, a first conductive portion formed on the first surface of the substrate and made of a first plated cover layer, a second conductive portion formed on the second surface of the substrate and made of a second plated cover layer, the second conductive portion being positioned opposite the first conductive portion, and multiple first through-hole conductors made of conductors formed in the multiple first penetrating holes, respectively, the multiple first through-hole conductors connecting the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion and the first through-hole conductors form a first through-hole connection section which sets up either a power-source through-hole conductor or a ground through-hole conductor.

Abstract: A secondary battery, including a bare cell, a protective circuit module (PCM) disposed on a top surface of the bare cell, the PCM comprising an external terminal a top surface thereof, and a printed circuit board (PCB) terminal disposed on the external terminal, the PCB terminal being electrically connected to the external terminal and an external device.

Abstract: The present invention relates to a method of producing an electrically conducting via in a substrate and to a substrate produced thereby. In particular, in one embodiment, the present invention relates to a substrate, such as a printed circuit board having one or several metal-free electrically conducting vias.

Abstract: A multilayer printed circuit board has an IC chip included in a core substrate in advance, and an intermediate layer provided on a pad of the IC chip. Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the intermediate layer made of copper on the die pad, it is possible to prevent resin residues on the pad and to improve connection characteristics between the pad and a via hole, and to improve reliability.

Abstract: A multilayer printed circuit board has an IC chip included in a core substrate in advance and a mediate layer provided on a pad of the IC chip. Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the mediate layer made of copper on the die pad, it is possible to prevent resin residues on the pad and to improve connection characteristics between the pad and a via hole and reliability.

Abstract: An electrical connection arrangement includes an IC package, and a PCB having a plurality of receiving holes for receiving a plurality of contacts therein. The contact having a contacting portion engaged with the IC package that seated upon the PCB. A retaining device is provided for securing the IC package onto the PCB. Since there is no socket utilized in the present invention, the total profile of the arrangement and the cost are effectively reduced.

Abstract: A multilayer printed circuit board has an IC chip included in a core substrate in advance and a mediate layer provided on a pad of the IC chip. Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the mediate layer made of copper on the die pad, it is possible to prevent resin residues on the pad and to improve connection characteristics between the pad and a via hole and reliability.

Abstract: A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.

Abstract: A printed circuit board (“PCB”) (100) includes a first routing layer (110), a second routing layer (120) and a via hole structure (150) electrically connecting the two routing layers. The via hole structure (150) includes a connecting hole (158) extending between the first routing layer (110) and the second routing layer (120), an inner conductor (154) positioned in the connecting hole (158), an outer conductor (152) substantially surrounds the inner conductor (154), and an insulating medium (156) positioned between the inner conductor and the outer conductor. The outer conductor (152) is insulated from the inner conductor (154), the outer conductor (152) is configured to connected to the ground, and the inner conductor (154) is configured to transmit signals.

Abstract: An electronic circuit unit includes a multi-layer substrate in which high frequency circuits are provided on two different layers and a ground layer is formed between the two layers, and grounding lands connected to peripheral conductive members through connection bars formed on a plurality of layers of the multi-layer substrate. The grounding lands are connected to each other through a via hole and conducted to the ground layer, and the connection bars protruding radially outward from at least two grounding lands provided on different layers are arranged in different directions with respect to a circumferential direction such that the connection bars do not overlap each other along a thickness direction of the multi-layer substrate.

Abstract: [Subject Matter] To provide a method for manufacturing a wiring substrate where rigidity is enhanced in an insulative portion made by oxidizing aluminum. [Solution(s)] Aluminum oxide insulative portion 24 is formed on aluminum plate 20 as shown in FIG. 1(A) through anodic oxidation (FIG. 1(C)). Then, holes (nano-holes) (24h) in aluminum oxide 24 are filled with resin 30 (FIG. 1(E)). Accordingly, the rigidity (strength) of insulative portion 24 will be enhanced and cracking will not occur during heat cycles. Also, the insulation reliability of aluminum oxide will increase, and short circuiting may be prevented at through holes 26 (aluminum portions) separated by aluminum oxide 24.

Abstract: A method for fabricating a packaging substrate includes: stacking two metal layers; encapsulating the two metal layers with assistant dielectric layers; forming built-up structures on the assistant dielectric layers, respectively; and separating the built-up structures along the interface between the two metal layers so as to form two packaging substrates. Owing to the adhesive characteristic of the assistant dielectric layers, the two metal layers are unlikely to separate from each other during formation of the built-up structures. But after portions of the dielectric layer around the periphery of the metal layers are cut and removed, the two metal layers can be readily separated from each other. The two metal layers can be patterned to form wiring layers, metal bumps, or supporting structures to avoid waste of materials. A packaging substrate and a fabrication method thereof are provided.

Abstract: Disclosed herein is a printed circuit board. When power layers for supplying different voltages are sequentially stacked, a first EBG cell formed between a first power layer and a ground layer is arranged within a second EBG cell formed between a second power layer and the ground layer to allow the first EBG cell and the second EBG cell to have a double EBG structure. Accordingly, the present invention can prevent a DC open state while preventing noise and realizing band-stop characteristics.

Abstract: Disclosed is a printed circuit board, which includes a first circuit layer embedded in one surface an insulating layer and including a bump pad and a wire bonding pad, thus realizing a high-density wire bonding pad. A semiconductor device including the printed circuit board and a method of manufacturing the printed circuit board are also provided.

Abstract: A method is disclosed for fabricating a PCB so that is can easily be determined if a via in the PCB has not been counterbored to a desired depth. A PCB fabricated according to the method also is disclosed.

Abstract: A circuit subassembly, comprising a dielectric layer formed from a dielectric composition comprising, based on the total volume of the composition: about 15 to about 65 volume percent of a dielectric filler; and about 35 to about 85 volume percent of a thermosetting composition comprising: a poly(arylene ether), and a carboxy-functionalized polybutadiene or polyisoprene polymer.

Abstract: An electronic device includes: a first substrate; and a second substrate on which the first substrate is mounted and which is electrically connected to the first substrate in at least one predetermined area. The predetermined area includes at least two through vias running through the first substrate, and an interconnect provided in the second substrate. The at least two through vias are electrically connected together via the interconnect.

Abstract: The present invention relates to a multilayer ceramic substrate including: a ceramic stacked structure in which multiple ceramic layers are stacked and interconnected to one another through vias provided in respective ceramic layers, the ceramic stacked structure having surface reforming layers 111a formed by removal of glass component on the surfaces of upper and lower parts of the ceramic layers; and contact pads formed on a top surface and a bottom surface of the ceramic stacked structure so as to be electrically connected to the vias.