Abstract: Provided is a method for manufacturing a circuit board provided with metal posts formed on at least one surface of the circuit board, the method including preparing a substrate made of a conductive material, performing a first selective etching a first surface of the substrate in regions corresponding to insulating portions of a first circuit pattern, laminating a first insulating layer over the first surface of the substrate, and performing a second etching on a second surface opposite of the first surface of the substrate, thereby forming the metal posts and the first circuit.

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.

Abstract: A circuit board structure including a dielectric layer, a fine circuit pattern and a patterned conductive layer is provided, wherein the fine circuit pattern is embedded in a surface of the dielectric layer, and the patterned conductive layer is disposed on another surface of the dielectric layer and protrudes therefrom.

Abstract: A printed wiring board including a rigid multilayer board, a first substrate having multiple conductors, and a second substrate having multiple conductors electrically connected to the conductors of the first substrate. The conductors of the second substrate have an existing density which is set higher than an existing density of the conductors of the first substrate, and the first substrate and/or the second substrate is embedded in the rigid multilayer board.

Abstract: A via is provided on a printed circuit board with at least one additional depression encompassing the via, such that the via passes through a portion of the depression. Solder can pool in the depression, allowing for a stronger mechanical bond and eliminating many issues with respect to a lack of coplanarity between a lead and the printed circuit board. The depression can be provided with plugged and unplugged vias, and improves the mountings associated with both.

Abstract: A method is disclosed for fabricating a PCB so that is can easily be determined if a via in the PCB has not been counterbored to a desired depth. A PCB fabricated according to the method also is disclosed.

Abstract: A printed wiring board includes a substrate having a first surface, a second surface on the opposite side of the first surface and a through-hole extending between the first and second surfaces, a first conductive circuit formed on the first surface of the substrate, a second conductive circuit formed on the second surface of the substrate, and a through-hole conductor filling the through-hole and connecting the first and second conductive circuits. The through-hole has a first opening portion tapering from the first surface toward the second surface and a second opening portion tapering from the second surface toward the first surface. The substrate is made of a resin and a reinforcing material portion in the resin. The reinforcing material portion has a protruding portion protruding into the through-hole at the intersection of the first and second opening portions. The protruding portion encroaches into the through-hole conductor.

Abstract: In first and second electrode pads adjacent to each other formed over a multilayer substrate, the first electrode pad is connected with a first conductive via and a first internal layer conductive line successively. The second electrode pad is connected with a surface layer conductive line, third electrode pad, second conductive via, and second internal layer conductive line of the multilayer substrate. A ground conductive via or a power source conductive via is disposed between the first internal layer conductive line and the surface layer conductive line. A ground conductive line layer or power source conductive line layer is disposed between a first formation layer where the first internal layer conductive line is formed and a second formation layer where the second internal layer conductive line is formed. The first and second electrode pads are connected with the electrode pads formed on the surface of first and second optical devices.

Abstract: A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.

Abstract: An electronic device having a press-fit connection for connecting a connector and an electronic part mounted on a printed circuit board which is possible to enable high density mounting. Viewing the printed circuit board from an upper surface, between adjacent through holes on which a compressive force acts upon insertion of the press-fit terminal, among the large number of through holes, a land or a conductor film connected to the conductor film formed on the inner wall surface of the through hole or the conductor film not connected to the conductor film formed on the inner wall surface of the through hole, formed in the circuit board held between the top layer circuit board and the bottom layer circuit board, exists in a width equal to or wider than the diameter of the through hole.

Abstract: The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.

Abstract: A circuit board includes a substrate having upper and lower sides, and first and second conductive vias extending between the upper and lower sides. The first and second conductive vias include circular outer profiles. The circuit board also includes a differential pair of conductive traces, which includes a first conductive trace having first upper and lower segments disposed on the upper and lower sides, respectively. The first upper and lower segments are electrically connected together through the first conductive via. The first upper segment is curved around the second conductive via such that the first upper segment follows the circular outer profile of the second conductive via. The differential pair of conductive traces also includes a second conductive trace having second upper and lower segments disposed on the upper and lower sides, respectively. The second upper and lower segments are electrically connected together through the second conductive via.

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole for a via conductor, a conductive circuit formed on one surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and having a protruding portion protruding from the other surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the protruding portion of the via conductor. The via conductor is connected to the conductive circuit and has a first conductive layer formed on the side wall of the penetrating hole and a plated layer filling the penetrating hole.

Abstract: A wiring board has a wiring member, a first reinforcing member and a second reinforcing member. The wiring member has wiring layers and insulating layers which are stacked, and the wiring layers include a first connecting electrode formed on a surface of the wiring member and a second connecting electrode formed on a back surface of the wiring member. A pin is formed on the second connecting electrode. The second reinforcing member is formed by a resin and serves to reinforce the wiring member. The first reinforcing member is formed on the whole back surface of the wiring member except for the pin provided on the second connecting electrode.

Abstract: A method is for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions together.

Abstract: Printed circuit boards are provided with embedded components. The embedded components may be mounted within recesses in the surface of a printed circuit board substrate. The printed circuit board substrate may have grooves and buried channels in which wires may be mounted. Recesses may be provided with solder pads to which the wires may be soldered or attached with conductive adhesive. An integrated switch may be provided in an opening within a printed circuit board substrate. The integrated switch may have a dome switch member that is mounted within the opening. A cover member for the switch may be formed from a flexible layer that covers the dome switch member. Terminals for the integrated switch may be formed from conductive structures in an interior printed circuit board layer. Interconnects may be used to electrically connect embedded components such as switches, integrated circuits, solder pads for wires, and other devices.

Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract: A multiple-layer wiring substrate having a first conductive layer; an interlayer insulating layer; and a second conductive layer is disclosed, wherein the interlayer insulating layer includes a material whose surface energy is changed by receiving energy, and has a first region which does not include a contact hole and a second region which is formed such that its surface energy is higher than that of the first region, wherein a region within the contact hole of the first conductive layer has surface energy which is higher than surface energy of the second region of the interlayer insulating layer, and wherein the second conductive layer is formed by laminating, wherein the second conductive layer is in contact with the second region of the interlayer insulating layer along the second region, and is connected to the first conductive layer via the contact hole.

Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Abstract: A method for fabricating a carrier substrate, a method for fabricating a printed circuit board using the carrier substrate and related printed circuit board. The method for fabricating the carrier substrate includes: providing an insulating base material with a copper foil layer formed on at least one surface thereof; stacking a metal layer having a length shorter than that of the copper foil layer on the copper foil layer; and forming an insulating layer on the metal layer.

Abstract: A printed circuit board including first and second signal pads located on a top surface of the printed circuit board and arranged to transmit a first differential signal, first and second signal vias extending through the printed circuit board and arranged to transmit the first differential signal, and a first ground plane located on a layer below the top surface of the printed circuit board and including an antipad that encompasses the first and second signal pads and the first and second signal vias when viewed in plan.

Abstract: An electrical system including (1) a printed circuit board including first and second signal pads located on a top surface of the printed circuit board and arranged to transmit a first differential signal, first and second signal vias extending through the printed circuit board and arranged to transmit the first differential signal, a first signal trace located on the top surface of the printed circuit board and connecting the first signal pad and the first signal via, and a second signal trace located on the top surface of the printed circuit board and connecting the second signal pad and the second signal via; and (2) a connector including first and second signal contacts arranged to transmit the first differential signal. The first differential signal transmitted through the printed circuit board and the connector has a common central axis.

Abstract: A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.

Abstract: A printed circuit board (PCB) includes two layers, two signal transmission traces, and a vertical interconnect access (via). The signal transmission traces are respectively arranged on the layers. The signal transmission traces are electrically connected to each other through the via. A centerline of the via with a vertical line of the layers form an acute angle ?, the angle ? is less than cos?1[(Lv2?Lt2)/(Lv2+Lt2)]. Wherein Lt is loss of the two signal transmitting traces in a unit length, and Lv is loss of the via in a unit length.

Abstract: A circuit member for a vehicle-mountable junction box is accommodated in the vehicle-mountable junction box. The circuit member is a metal core board including a metal core plate as a core. The core plate includes a separated part which is separated from a main part by a separating groove filled with an insulating material. Electronic components are mounted on both of a part including the main part and a part including the separated part.

Abstract: A printed wiring board includes an interlayer resin insulation layer having the first surface, the second surface on the opposite side of the first surface, and a penetrating hole for a via conductor, a conductive circuit formed on the first surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and connected to the conductive circuit on the first surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the via conductor exposed from the second surface of the interlayer resin insulation layer through the penetrating hole. The via conductor is made of a first conductive layer formed on the side wall of the penetrating hole and a plated-metal filling the penetrating hole. The surface of the via conductor is recessed from the second surface of the interlayer resin insulation layer.

Abstract: A copper-clad laminate of a highly-elastic glass fabric base material/thermosetting resin formed of prepreg obtained by impregnating a glass fabric base material made of a glass woven fabric having a thickness of 25 to 150 ?m, a weight of 15 to 165 g/m2 and a gas permeability of 1 to 20 cm3/cm2/sec. with a thermosetting resin composition and drying it.

Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

Abstract: Using developed photo-resist materials at the side walls of silicon substrates, the preferred embodiments of the present invention improve alignment accuracy of stacked substrates. Such alignment accuracy improves the area efficiency of side-wall connections as well as through-hole connections. The parasitic impedances of stacked substrate connections are also improved.

Abstract: A sub-component circuit board may be electrically and mechanically connected to a higher order circuit board using one or more leads extending from a lead frame embedded in the sub-component circuit board. The sub-component board is produced as a layered assembly with the embedded lead frame at the core. One or more dielectric layers and one or more circuitry layers are provided over the lead frame and then bonded using heat and pressure. Apertures in the dielectric and circuitry layers define a perimeter of the circuit board where the leads of the lead frame are exposed. The lead frame connects to the circuitry layer(s) using plated vias.

Abstract: A modified 0402 footprint for a PCB, including: at least two padstacks each having a minimum area consistent with the 0402 standard; and each padstack modified on at least two corners such that the padstack's footprint can be placed beneath a ball grid array (‘BGA’), the BGA having approximately a 1 millimeter pitch, and such that the padstack may be placed at least at a minimum distance away from a closest via in the PCB, wherein each padstack has a trace to a via not directly under a padstack in the PCB and each padstack has no via within the padstack.

Abstract: An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves.

Abstract: A lid for a MEMS device and the relative manufacturing method. The lid includes: a first board with opposite first and second surfaces having first and second metal layers disposed thereon, respectively, wherein a through cavity extends through the first board and the first and second metal layers; a second board with opposite third and fourth surfaces; an adhesive layer sandwiched between the second surface of the first board and the third surface of the second board to couple the first and second boards together such that the through cavity is closed by the second board, thereby forming a recess; and a first conductor layer coating the bottom and the side surfaces of the recess.

Abstract: Methods of backdrilling printed circuit boards (PCBs) to remove via stubs and related apparatuses. The method may include removing a via stub through a combination of backdrilling and chemical etching. The backdrilling may remove a masking layer from the via stub. Portions of an underlying layer may remain in the region of the via stub after the backdrilling is completed. The remaining portions of the underlying layer may be removed in a subsequent etching process thereby removing the via stub from the PCB. As the backdrilling step may be used for the limited purpose of removing the outer layer and portions of the underlying layer remaining in the via can be tolerated, the diameter of the backdrilling need not be as large as traditional backdrilling where all layers within the via must be ensured of being completely removed.

Abstract: An interconnect scheme includes a conductive ink forming a plurality of conductive regions, and a dielectric ink occupying spaces between the conductive regions. The conductive ink and the dielectric ink have substantially identical optical, acoustic, and x-ray absorption properties, thereby making the interconnect scheme tamper-resistant and/or difficult to identify and reverse-engineer using conventional detection methods.

Abstract: A printed wiring board has a packaging substrate having multiple pads, and a transmission substrate mounted on the multiple pads of the packaging substrate. The packaging substrate has a pad group constituted of pads which mount an electronic component, the multiple pads mounting the transmission substrate includes a first pad positioned in a peripheral portion of the packaging substrate and a second pad positioned between the first pad and the pad group, the second pad is electrically connected to a signal pad of the pads in the pad group, and the transmission substrate includes a horizontal wiring which electrically connects the second pad and the first pad and which transmits a signal between the second pad and the first pad.

Abstract: A substrate is provided that includes a plurality of substrate layers and a plural diameter via having a first via portion and a second via portion. The first via portion is formed in a first substrate layer, has a first diameter, and extends along a first axis. The second via portion is formed in a second substrate layer, has a second diameter that is different than the first diameter of the first via portion, and extends along a second axis that is offset from the first axis of the first via portion. Optionally, the first via portion and the second via portion may have a common edge that is spaced the same distance from an edge of another via extending through the substrate.

Abstract: An approach is provided in detecting plated-through hole defects in printed circuit boards (PCBs). The printed circuit board is exposed to a modified-silane solution. The modified-silane solution has a luminescent moiety and the modified-silane solution binds to exposed glass within a glass fiber layer of the printed circuit board. Plated-through hole defects are identified in the printed circuit board by detecting a luminescence at a surface location of the printed circuit board. Each surface location where the luminescence is detected corresponds to one of the plated-through hole defects.

Abstract: A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced.

Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract: The present invention relates to a layered structure assembly (1) for a DC to AC inverter comprising: a first layered structure (10) with first (12) and second (13) conductive layers, a second layered structure (14) with third (16) and fourth (17) conductive layers, and at least one connector (21) providing a low resistance/inductance interconnection between layered structures (10, 14), the connecter (21) comprising a rod (23) inside a sleeve (26).

Abstract: A printed circuit board for mounting electronic parts thereon includes a ground portion formed on the printed circuit board and connected to an outer ground. A plurality of conductive ground layers are stacked so as to interpose an insulation layer therebetween. An upper conductive ground layer includes first and second conductive ground portions. The first and second ground portions are connected by a connecting element. Another conductive ground layer under the upper conductive ground layer is grounded via the first and second ground portions of the upper conductive ground layer via a through hole provided in the ground portion.

Abstract: A method of manufacturing a printed circuit board is disclosed. A conductive metal layer is formed on a first surface of a dielectric substrate. One or more vias are formed through the substrate. A conductive metal layer is formed on the first surface of the substrate and is patterned to form conductive traces on the first surface of the substrate. A plating mask is formed on the second surface of the substrate. One or more openings are formed in the plating mask to correspond to the location of the via(s). Conductive metal is deposited in the via(s) sufficient to substantially fill the via(s) and make contact with the conductive metal layer on the first surface and substantially to the level of the plating mask. The plating mask is removed from the substrate such that one or more conductive posts extend outwardly from the second surface of the substrate.

Abstract: Disclosed are a carrier substrate including an insulating base material with a copper foil layer formed on at least one surface thereof, a metal layer formed on the copper layer and having a length shorter than that of the copper foil layer, and an insulating layer formed on the metal layer, a fabrication method thereof, a printed circuit board (PCB) using the same, and a fabrication method thereof. Because there is no land at the via and core in the substrate, because a circuit pattern connected with the via can be formed to be finer, so the circuit pattern can be highly integrated and the substrate can become thinner. Thus, a printed circuit board (PCB) having a smaller size and reduced number of layers can be fabricated.

Abstract: A structure with electronic component mounted therein includes a wiring board on which an electronic component is mounted at least on its first face, resin provided at least between the electronic component and the wiring board, and a plurality of holes formed in the wiring board at region corresponding to a mounting position of the electronic component. The holes are filled with the resin. This suppresses warpage of the structure with electronic component mounted therein, and also improves reliability by reducing a stress applied to a bonding section between the wiring board and the electronic component.

Abstract: An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: The disclosed structure (10) is provided with: at least three conductors (111, 131, 151) which face one-another; a through-via (101) which passes through each of the conductors (111, 131, 151); openings (112, 152) which are provided so as to surround the circumference of the through-via (101); and conductor elements (121, 141) which are located in different layers to those in which the conductors (111, 131, 151) are located, and which are connected to the through-via (101). Facing opening 112 is conductor element 121, which is larger than said opening (112), and facing opening 152 is conductor element 141, which is larger than said opening (152).

Abstract: A PWB having a plurality of through holes into which electronic parts' leads are inserted, and metal plated lands formed around the through holes. The metal plated lands are polygon in which the number of sides is an even number and each pair of facing sides are parallel, and the lands have circular concaves at all the corners and the sides of polygon are arranged to be parallel to the sides of the neighboring metal plated lands.

Abstract: A method of manufacturing a printed circuit board having a flow preventing dam, including: applying a dry film resist on a base substrate having a solder pad, and then primarily exposing the dry film resist to light; secondarily exposing the primarily exposed dry film resist formed on a peripheral area of the base substrate to light, thus forming a flow preventing dam; removing the unexposed dry film resist to expose the solder pad, thus forming an opening; printing the opening with a solder paste, and then forming a solder bump through a reflow process; and removing the primarily exposed dry film resist.