Hollow (e.g., Plated Cylindrical Hole) Patents (Class 174/266)
  • Publication number: 20130299227
    Abstract: The present invention relates to a laminated body for forming a printed circuit board comprising: a separation member in which first conductive layers and second conductive layers separable from each other are sequentially provided on each of upper and lower surfaces of a separating-insulation member; a laminating-insulation member sequentially laminated on each of the upper and lower surfaces of the separation member; and a conductive layer sequentially laminated on each of upper and lower surfaces of the insulation member, a printed circuit board comprising the laminated body, and a method of manufacturing the same. The present invention provides the new multi-layer printed circuit board to which various designs, such as a double-sided structure or an unbalanced structure, are applicable while overcoming an application limitation of a single-sided printed circuit board structure in the related art, thereby improving productivity and economic feasibility.
    Type: Application
    Filed: November 4, 2011
    Publication date: November 14, 2013
    Applicant: DOOSAN CORPORATION
    Inventors: Eun Yong Chung, Kyung Woon Cho, Tae Sik Eo, Woo Hyun Noh
  • Patent number: 8581114
    Abstract: A packaged structure having a magnetic component and a method of manufacturing the same are provided. The packaged structure includes an insulating substrate having a ring-typed recess, an island portion and a surrounding portion defined by the ring-typed recess, wherein the ring-typed recess is laterally between the island portion and the surrounding portion.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: November 12, 2013
    Assignees: Planarmag, Inc., Mutual-Tek Industries Co., Ltd.
    Inventors: William Lee Harrison, Jung-Chien Chang
  • Patent number: 8580682
    Abstract: A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Yung-Chi Lin, Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20130293482
    Abstract: This disclosure provides systems, methods and apparatus for transparent conductive vias in a transparent substrate. In one aspect, a transparent conductive via extends through a transparent substrate and electrically connects a topside conductor on a top surface of the transparent substrate and a bottom side conductor on a bottom surface of the transparent substrate. In another aspect, a transparent conductive via extends at least partially through a transparent substrate and is in electrical communication with a topside conductor on a top surface of the transparent substrate. In another aspect, a method of forming a transparent through-substrate via is provided.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: David William Burns, Kristopher Andrew Lavery
  • Publication number: 20130284508
    Abstract: A printed circuit board (PCB) includes a power layer and a signal layer. A signal line is arranged on the signal layer. A power via extends through the power layer and the signal layer, and is electrically connected to the power layer and the signal layer. A number of through holes is defined in the PCB, through the power layer and the signal layer, and arranged between the signal line and the power via. The through holes are insulated from the power via. The inside wall of the power via is made of conductive material.
    Type: Application
    Filed: August 1, 2012
    Publication date: October 31, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEI-CHIEH CHOU, CHUN-JEN CHEN, DUEN-YI HO, TSUNG-SHENG HUANG, PO-CHUAN HSIEH, CHUN-NENG LIAO
  • Publication number: 20130277099
    Abstract: An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: XILINX, INC.
    Inventor: Paul Y. Wu
  • Patent number: 8563873
    Abstract: A method for manufacturing a substrate with a metal film includes preparing a first insulation layer having first and second surfaces, forming a first conductive circuit on the first surface of the first insulation layer, forming on the first surface of the first insulation layer and on the first conductive circuit a second insulation layer having first and second surfaces, forming in the second insulation layer a penetrating hole tapering from the first surface toward the first conductive circuit, forming on the inner wall of the penetrating hole, a composition containing a polymerization initiator and a polymerizable compound, providing a polymer on the inner wall of the penetrating hole by irradiating the composition, applying a plating catalyst on the polymer, and forming a plated-metal film on the inner wall of the penetrating hole. The first surface of the first insulation layer faces the second surface of the second insulation layer.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 22, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Ayao Niki, Atsushi Ishida, Ryojiro Tominaga
  • Publication number: 20130271907
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Application
    Filed: August 16, 2011
    Publication date: October 17, 2013
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Publication number: 20130269996
    Abstract: A structure of via hole of electrical circuit board includes an adhesive layer and a conductor layer that are formed after wiring is formed on a carrier board. At least one through hole extends in a vertical direction through the carrier board, the wiring, the adhesive layer, and the conductor layer and forms a hole wall surface. The conductor layer shows a height difference with respect to an exposed zone of the circuit trace in the vertical direction. A conductive cover section covers the conductor layer and the hole wall surface of the through hole. The carrier board is a single-sided board, a double-sided board, a multi-layered board, or a combination thereof, and the single-sided board, the double-sided board, and multi-layered board can be flexible boards, rigid boards, or composite boards combining flexible and rigid boards.
    Type: Application
    Filed: July 13, 2012
    Publication date: October 17, 2013
    Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.
    Inventors: GWUN-JIN LIN, KUO-FU SU
  • Patent number: 8552570
    Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Masaya Kawano, Kouji Soejima, Yoichiro Kurita
  • Patent number: 8552311
    Abstract: An electrical feedthrough includes a ceramic body and a ribbon via extending through the ceramic body, an interface between the ribbon via and the ceramic body being sealed using partial transient liquid phase bonding. The ribbon via extends out of the ceramic body and makes an electrical connection with an external device.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: October 8, 2013
    Assignee: Advanced Bionics
    Inventors: Kurt J. Koester, Timothy Beerling
  • Publication number: 20130260182
    Abstract: A printed circuit board (PCB) for an energy storage module is disclosed which includes a first side having a plurality of low current traces useful for monitoring and balancing applications and a second side coated with high current traces, useful for current or power transmission purposes. Vias connect the high current traces to the low current traces thereby electrically connecting both sides of the board together. The disclosed PCB is particularly useful for energy storage modules whereby monitoring and/or balancing of the modules is required in addition to the transmission of high current levels for power applications.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: Caterpillar, Inc.
    Inventors: Andrew A. Knitt, Wellington Ying-Wei Kwok
  • Patent number: 8545051
    Abstract: A substrate for a lighting apparatus includes one or more light-emitting elements mounted thereon. The substrate includes a surface on which the plurality of light-emitting elements are mounted. Additionally, the substrate includes heat conductive elements for conducting heat from the one or more light-emitting elements, the heat conductive elements including heat conductive holes extending through a non-electrically conducting layer formed on a first surface of the substrate and an entirety of the substrate and a heat conductive layer formed on a surface of the substrate opposite the first surface.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 1, 2013
    Assignees: Toshiba Lighting & Technology Corporation, Kabushiki Kaisha Toshiba
    Inventors: Takayoshi Moriyama, Kazunari Higuchi, Sumio Hashimoto, Shinichi Kumashiro
  • Publication number: 20130248237
    Abstract: A printed circuit board (PCB) includes at least two vias and at least two bonding pads corresponding to the vias. Each bonding pad is arranged on the surface of the PCB around the corresponding one of the at least two vias. Between two adjacent bonding pads, a through hole is arranged for preventing molten solder overflowing from one bonding pad to the other.
    Type: Application
    Filed: August 8, 2012
    Publication date: September 26, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD .
    Inventors: JIE-SONG ZHOU, XING-HUA TANG
  • Publication number: 20130250533
    Abstract: A method of making a wiring substrate includes forming a first metal layer on a surface of a support member, the first metal layer having at least one columnar through hole that exposes the surface of the support member, forming a columnar metal layer that fills the columnar through hole, forming an insulating layer on the columnar metal layer and on the first metal layer, forming an interconnection layer on a first surface of the insulating layer such that the interconnection layer is electrically connected to the columnar metal layer through the insulating layer, and forming a protruding part including at least part of the columnar metal layer by removing at least the support member and the first metal layer, the protruding part protruding from a second surface of the insulating layer opposite the first surface and serving as at least part of a connection terminal of the wiring substrate.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 26, 2013
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kotaro KODANI, Junichi Nakamura
  • Publication number: 20130240259
    Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Hideaki YOSHIMURA
  • Patent number: 8536464
    Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.
    Type: Grant
    Filed: May 26, 2008
    Date of Patent: September 17, 2013
    Assignee: NEC Corporation
    Inventors: Taras Kushta, Jun Sakai, Hikaru Kouta
  • Publication number: 20130233609
    Abstract: A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded metal wires. A sealing material is added to sidewalls of a volume having the plurality of extruded metal wires within, with the first and second plattens as end plates to form a holding volume. The holding volume is filled with a filling material. The filling material is heated to a sufficient temperature to form a heat treated filled volume. After removing the sealing material, the heat treated filled volume is sawed into a plurality of slices having a predetermined thickness to form a plurality of interposer substrates having a plurality of feed-thru conducting features provided by the plurality of extruded metal wires.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 12, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: STEVEN KUMMERL
  • Publication number: 20130233608
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20130235542
    Abstract: In an example embodiment, an electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: FINISAR CORPORATION
    Inventors: Yunpeng SONG, Yongsheng LIU, Hongyu DENG
  • Publication number: 20130220691
    Abstract: Provided is a multilayer wiring substrate comprising a first build-up layer and a second build-up layer including at least one insulating layer and at least one conductor layer, and a supporting substrate that supports the first and second build-up layers on the upper surface and the lower surface thereof, respectively. The multilayer wiring substrate includes a through hole extending between the upper surface side and the lower surface side of the supporting substrate, the through hole including openings on an upper and a lower end side thereof, a through hole conductor which is formed on the inner circumferential surface of the through hole, a conductor layer which is formed as to cover the opening on the upper end side of the through hole, and a conductor layer which is formed in a periphery of the opening on the lower end side of the through hole without covering the opening.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 29, 2013
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventor: NGK SPARK PLUG CO., LTD.
  • Publication number: 20130222003
    Abstract: A wiring board and a probe card using the wiring board which respond to a demand for improving electrical reliability.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 29, 2013
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: KYOCERA SLC Technologies Corporation
  • Publication number: 20130213705
    Abstract: A method of fabricating a printed-wiring board, includes: forming a through-hole across a thickness of a printed-wiring board, the forming of the through-hole including forming a first opening part having a first diameter, forming a second opening part having a second diameter, and forming a third opening part provided between the first opening part and the second opening part, wherein the second diameter is larger than the first diameter, and the third opening part is formed in a tapered shape whose diameter decreases toward the first opening part from the second opening part.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 22, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Publication number: 20130214408
    Abstract: There are disclosed herein various implementations of an interposer for use in semiconductor packaging. One exemplary implementation comprises a conductive post formed from a wire bond. A first end of the conductive post is mechanically joined to a conductive pad on a first surface of the interposer, while a second end of the conductive post is capable of making electrical connection to a contact body on an active surface of a semiconductor die. Such an interposer may include a rigid or flexible interposer dielectric. In one exemplary implementation, the interposer dielectric has a via formed therein, the conductive post being situated in the via and extending through a second surface of the interposer opposite the first surface.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8513539
    Abstract: A wiring board has a base substrate, a conductive pattern formed on the base substrate, an insulation layer formed on the conductive pattern and the base substrate and including a resin-impregnated inorganic cloth, a conductive pattern formed on the insulating layer, a via formed in the insulation layer and connecting the conductive pattern formed on the base substrate and the conductive pattern formed on the insulating layer, and a through-hole connected to the conductive pattern formed on the base substrate, penetrating through the base substrate and having a hole diameter in a range of 10 ?m to 150 ?m.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 20, 2013
    Assignee: Ibiden Co., Ltd.
    Inventor: Michimasa Takahashi
  • Patent number: 8508037
    Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: August 13, 2013
    Assignee: Intel Corporation
    Inventors: Mathew J. Manusharow, Mark S. Hlad, Ravi K. Nalla
  • Publication number: 20130199833
    Abstract: Disclosed herein is a circuit board including: a base substrate including a via for power and a via pad for power connected to the via for power; and an insulating layer formed on the base substrate and including a dummy pattern formed in a region facing the via pad for power.
    Type: Application
    Filed: December 11, 2012
    Publication date: August 8, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Samsung Electro-Mechanics Co., Ltd.
  • Publication number: 20130199834
    Abstract: A circuit board (1) is provided comprising a plurality of insulating layers, at least one ground layer and at least one layer comprising signal traces. The circuit board comprises at least a first conductive via (17) and a second conductive via (17). The first conductive via and the second conductive via penetrate through at least a first insulating layer of the plurality of insulating layers and are connected to a signal trace. The first conductive via and the second conductive via are arranged adjacent each other. At least in the first insulating layer the first conductive via and the second conductive via are separated in a first direction of separation (R) by a first adjustment portion comprising a dielectric material property different from the first insulating layer.
    Type: Application
    Filed: June 28, 2011
    Publication date: August 8, 2013
    Applicant: FCI
    Inventors: Jan De Geest, Stefaan Hendrik Jozef Sercu
  • Patent number: 8502086
    Abstract: Wiring board bases 2 to 4 are provided with: insulating substrates 1a to 4a having conductive layers 1b to 4b provided on one surfaces thereof, respectively; through-holes 2e to 4e which are arranged on the insulating substrates and reach the conductive layers from the other surfaces; and conductive vias 2d to 4d connected to the conductive layers by filling the through-holes with a conductive paste. In a method for manufacturing a laminated wiring board, at least one of the wiring board bases is stacked. Before the through-hole is filled with the conductive paste, a surface portion, in the through-hole, of the conductive layer is smoothed and a smooth surface portion 2g is formed.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: August 6, 2013
    Assignee: Fujikura Ltd.
    Inventor: Takaharu Hondo
  • Patent number: 8502085
    Abstract: A multi-layer substrate includes a plurality of substrate main bodies, a plurality of layers which are alternately layered with the main bodies, a signal via hole which is connected with a signal line and includes a signal column which passes through at least one substrate main body; and a sub via hole which includes a sub column which surrounds the signal column, and a pair of sub pads which extend from end parts of the sub column to be formed to the layers, the layers which are formed with the sub pads being disposed in the same layer as the layers which are formed with the signal line of the signal via hole, or being disposed outside the layers which are formed with the signal line which is connected with the signal via hole.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-seok Kim
  • Publication number: 20130193572
    Abstract: In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process.
    Type: Application
    Filed: January 31, 2013
    Publication date: August 1, 2013
    Applicant: MARVELL WORLD TRADE LTD.
    Inventor: MARVELL WORLD TRADE LTD.
  • Patent number: 8492659
    Abstract: The present invention provides a printed wiring board which can prevent a plating failure in a connection hole such as a via to be formed in the printed wiring board, thereby can enhance the connection reliability and a manufacturing method therefor. The printed wiring board 100 includes a thermosetting resin sheet 16 (insulation layer) having a via hole 20 (through hole) constituted by inner wall parts having different taper angles from each other, a copper foil 17 (conductor layer) provided on the thermosetting resin sheet 16, and a wiring pattern 13 (wiring layer) which is provided so as to be exposed from the via hole 20 and is electrically connected with the copper foil 17 through the via hole 20.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: July 23, 2013
    Assignee: TDK Corporation
    Inventors: Kenji Nagase, Hiroyuki Uematsu, Kenichi Kawabata
  • Patent number: 8476537
    Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 2, 2013
    Assignee: NEC Corporation
    Inventor: Taras Kushta
  • Publication number: 20130161084
    Abstract: In a printed wiring board including a first wiring layer and a second wiring layer provided via an insulator layer, at least three guard ground wirings extending along a pair of signal wirings provided in the first wiring layer and supplied with a ground potential are provided between the pair of signal wirings. Thus, crosstalk noise can be reduced without widening a wiring area between the pair of signal wirings.
    Type: Application
    Filed: September 16, 2011
    Publication date: June 27, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Seiji Hayashi
  • Publication number: 20130161083
    Abstract: A printed circuit board includes a substrate having a first surface, a first conductive circuit deposited on the first surface and a dielectric cover deposited on the first surface and covering at least a portion of the first conductive circuit. The dielectric cover has an edge and the first surface is exposed beyond the edge. A second conductive circuit is deposited on the dielectric cover and the substrate. The second conductive circuit spans the edge such that at least part of the second conductive circuit is deposited on the dielectric cover and at least part of the second conductive circuit is deposited on the first surface.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: Tyco Electronics Corporation
    Inventors: CHARLES RANDALL MALSTROM, Joseph D. Locondro, Michael Fredrick Laub, David Bruce Sarraf
  • Publication number: 20130153273
    Abstract: Disclosed herein are a stiffener and a method for manufacturing the same. The method includes: forming a metal film on an upper surface or a lower surface of a base layer; forming a plurality of via holes penetrating the base layer and the metal film; and forming a first plating film covering an external surface including an inner surface of each of the via holes. The double-sided conductive stiffener according to the present invention can support the device by being disposed on the lower surface of the FPCB, and provide a ground structure of the device through the metal film without using the conductive bond or the conductive tape.
    Type: Application
    Filed: October 26, 2012
    Publication date: June 20, 2013
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Samsung Electro-Mechanics Co., Ltd.
  • Patent number: 8466368
    Abstract: A high-frequency device according to one embodiment includes: a plate-like first dielectric substrate; a plurality of surface electrodes for capacitors which are formed on a surface of the first dielectric substrate; a rear face electrode for the capacitors which is formed on a rear face of the first dielectric substrate; a second dielectric substrate which is laminated on the first dielectric substrate and has an opening portion through which a plurality of the surface electrodes are exposed; a transmission line which is formed on a surface of the second dielectric substrate; and a conductive member to connect a plurality of the surface electrodes to the transmission line. The first dielectric substrate is made of dielectric material having a first dielectric constant. The second dielectric substrate is made of dielectric material having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: June 18, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutoshi Masuda
  • Publication number: 20130146670
    Abstract: In various embodiments, a chip card contact array arrangement is provided, having a carrier, a plurality of contact arrays which are arranged on a first side of the carrier, an electrically conductive structure which is arranged on a second side of the carrier, which is arranged opposite the first side of the carrier, a first plated-through hole and a second plated-through hole, wherein the first plated-through hole is coupled to the electrically conductive structure, a connecting structure which is arranged on the first side of the carrier, wherein the connecting structure connects the first plated-through hole to the second plated-through hole, the connecting structure having a longitudinal extent which runs parallel to a direction in which a contact-connection device on a reading device is moved relative to the plurality of contacts.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 13, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Infineon Technologies AG
  • Patent number: 8461461
    Abstract: The present invention relates to an embedded substrate having a circuit layer element with an oblique side surface and a method for making the same. The embedded substrate includes a dielectric layer and a circuit layer element. The dielectric layer has an upper surface and an accommodating groove. The circuit layer element is disposed in the accommodating groove. The circuit layer element has an upper surface, a chemical copper layer, a plating copper layer and an oblique side surface. The elevation of the upper surface is equal to or lower than that of the upper surface of the dielectric layer. The chemical copper layer includes palladium (Pd). The plating copper layer is disposed on the chemical copper layer. The oblique side surface is disposed on the upper surface of the circuit layer element, where is close to the wall of the accommodating groove, and extends downward from the upper surface of the circuit layer element to the wall of the accommodating groove.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: June 11, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chih-Cheng Lee
  • Patent number: 8461464
    Abstract: A circuit board having a plurality of first holes formed in a semiconductor substrate to extend therethrough; insulating layers formed on a back surface of the semiconductor substrate in the plurality of first holes, the insulating layers between the back surface and the first holes being differed in thickness; second holes formed in the insulating layers to communicate with the first holes; and an electro-conductive layer formed inside of the first holes and the second holes to extend through the semiconductor substrate.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 11, 2013
    Assignee: Sony Corporation
    Inventor: Takuya Nakamura
  • Publication number: 20130140074
    Abstract: Disclosed herein is a via hole plating method including a first plating step of performing a pattern plating on a via hole of a printed circuit board; and a second plating step of performing a pattern fill plating on the pattern plating, whereby a deviation in plating thickness at a high current density region may be decreased simultaneously with improving a via filling efficiency, thereby making it possible to significantly improve the quality of the printed circuit board.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 6, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: SAMSUNG ELECTRO-MECHANICS CO., LTD.
  • Publication number: 20130140070
    Abstract: An electrical communication system includes a printed circuit board (PCB) having first and second ground plates and a plurality of signal vias and a plurality of ground vias extending between and through the first and second ground plates. Each of the plurality of signal vias are electrically connected to a respective conductive trace on a surface of the PCB. Cables connect to the PCB at a right angle, with a connector attached to an opposite side of the PCB. Each cable has two signal wires and a ground wire extending therefrom. The two signal wires define a differential pair. The signal wires are symmetrical with respect to the ground wire. Each of the signal wires electrically connects to a respective one of the plurality of signal vias. The ground wire connects to one of the plurality of ground vias. The cables are offset with respect to one another on the first and second ground plates and within the PCB.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Craig William Clewell, Bruce Champion, Eric David Briant
  • Publication number: 20130126226
    Abstract: The invention relates to a method of manufacturing a support structure for supporting an article in a lithographic process, comprising: providing a substrate having an electrically conductive top layer provided on an insulator; patterning the conductive top layer to provide a patterned electrode structure; and oxidizing the conductive top layer, so as to provide a buried electrode structure having an insulating top surface. In this way a simple buried structure can be provided as electrode structure to conveniently provide an electrostatic clamp. The invention additionally relates to a correspondingly manufactured support structure for supporting an article in a lithographic process.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 23, 2013
    Applicant: NEDERLANDSE ORGANISATIE VOOR TOEGEPAST- NATUURWETENSCHAPPELIJK ONDERZOEK TNO
    Inventors: Norbertus Benedictus Koster, Marcus Hendrikus Meijerink, Edwin Te Sligte
  • Publication number: 20130118793
    Abstract: The present invention relates to a method for filling a through hole of a substrate with a metal. The method includes a step of preparing a bonded substrate including a first substrate having conductivity in at least a surface thereof and a second substrate having a through hole, both substrates being bonded to each other through a nonionic surfactant; a step of exposing, in the bonded surface of the bonded substrate, the conductive surface of the first substrate, which is positioned at the bottom of the through hole, by removing the nonionic surfactant positioned at the bottom of the through hole of the second substrate; and a step of filling the through hole with a metal by applying an electric field to the conductive surface of the first substrate.
    Type: Application
    Filed: July 4, 2011
    Publication date: May 16, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takayuki Teshima, Yutaka Setomoto
  • Publication number: 20130118794
    Abstract: A package substrate structure includes a substrate, a circuit layer formed on the substrate, and an ultra-thin seed layer made of an electrically conductive material and formed between the substrate and the circuit layer. The ultra-thin seed layer is advantageous to increase the adhesion between the metal bumps or the circuit lines of the circuit layer, and the substrate. Furthermore, because the seed layer is ultra thin, the metal bumps or the circuit lines on the package substrate can be made finer in line widths and line pitches, and the good yield of the substrate with fine circuit lines can be increased.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Inventor: Bo-Yu Tseng
  • Patent number: 8440917
    Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Publication number: 20130115428
    Abstract: The substrate gap supporter (30) according to one embodiment of the present invention comprises a body (31) having a hexahedron shape and made of an insulator, metal foils (32a) and (32b) installed on opposite side surfaces of the body (31) to expose the upper portions of both side surfaces and cover the lower portions of both side surfaces, and a substrate (210) attached to the bottom surface of the body (31). According to the present invention, the gap supporter can be made through an automated process, thus precisely controlling size. Since the gap supporter is attached to the surface of the substrate, there is little possibility for a height difference to occur. And also, because the gap supporter can be installed in an automated process, it is suitable for a mass production process.
    Type: Application
    Filed: September 9, 2010
    Publication date: May 9, 2013
    Applicant: GNE TECH CO., LTD
    Inventor: Jae Ku Kim
  • Publication number: 20130112471
    Abstract: Disclosed herein is a printed circuit board and a method of manufacturing the same. The printed circuit board includes preparing a base substrate; forming a pattern layer for forming via holes on the base substrate by printing ink for forming via holes; forming an insulating layer on the base substrate including the pattern layer for forming via holes; and removing the pattern layer for forming via holes.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 9, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Nam CHO, Jun Young KIM
  • Publication number: 20130112470
    Abstract: The present invention relates to circuit boards and, more specifically, circuit boards with vias (i.e. via holes) exhibiting reduced via capacitance. In one embodiment, the present invention provides a circuit board comprising a first electrically conductive trace, a second electrically conductive trace, a via hole including electrically conductive material thereon, and a coupling element that electrically connects the first trace to the second trace. The coupling element comprises a segment of the via hole that bridges the first trace and the second trace, wherein the via hole segment is a remainder of the via hole after removal of a portion of the via hole.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Eric R. Ao
  • Patent number: 8436254
    Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 7, 2013
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Po Yu, Han-Pei Huang